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| ? 2007-2012 microchip technology inc. ds70292g-page 1 dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 operating conditions 3.0v to 3.6v, -40oc to +150oc, dc to 20 mips 3.0v to 3.6v, -40oc to +125oc, dc to 40 mips clock management 2% internal oscillator programmable pll and oscillator clock sources fail-safe clock monitor (fscm) independent watchdog timer low-power management modes fast wake-up and start-up core performance up to 40 mips 16-bit dspic33f cpu single-cycle mul plus hardware divide advanced analog features 10/12-bit adc with 1.1msps/500 ksps rate: - up to 13 adc input channels and four s&h - flexible/independent trigger sources 150 ns comparators: - up to two analog comparator modules - 4-bit dac with two ranges for analog comparators input/output software remappable pin functions 5v-tolerant pins selectable open drain and internal pull-ups up to 5 ma overvoltage clamp current/pin multiple external interrupts system peripherals 16-bit dual channel 100 ksps audio dac cyclic redundancy check (crc) module up to five 16-bit and up to two 32-bit timers/ counters up to four input capture (ic) modules up to four output compare (oc) modules real-time clock and calendar (rtcc) module communication interfaces parallel master port (pmp) two uart modules (10 mbps) - supports lin 2.0 protocols - rs-232, rs-485, and irda ? support two 4-wire spi modules (15 mbps) enhanced can (ecan) module (1 mbaud) with 2.0b support i 2 c module (100k, 400k and 1mbaud) with smbus support data converter interface (dci) module with i 2 s codec support direct memory access (dma) 8-channel dma with no cpu stalls or overhead uart, spi, adc, ecan, ic, oc, int0 qualification and class b support aec-q100 revg (grade 0 -40oc to +150oc) class b safety library, iec 60730, vde certified debugger development support in-circuit and in-application programming two program breakpoints trace and run-time watch packages type spdip soic qfn-s qfn tqfp pin count 28 28 28 44 44 i/o pins 21 21 21 35 35 contact lead/pitch .100 1.27 0.65 0.65 0.80 dimensions .285x.135x1.365 7.50x2.05x17.9 6x6x0.9 8x8x0.9 10x10x1 note: all dimensions are in millimeters (mm) unless specified. 16-bit digital signal controllers (up to 128 kb flash and 16k sram) with advanced analog downloaded from: http:///
dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 2 ? 2007-2012 microchip technology inc. dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 product families the device names, pin counts, memory sizes, and peripheral availability of each device are listed below. the following pages show their pinout diagrams. table 1: dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 controller families device pins program flash memory (kbyte) ram (kbyte) (1) remappable peripheral rtcc i 2 c? crc generator 10-bit/12-bit adc (channels) 16-bit audio dac (pins) analog comparator (2 channels/voltage regulator) i/o pins packages remappable pins 16-bit timer (2) input capture output compare standard pwm data converter interface uart spi ecan? external interrupts (3) 8-bit parallel master port (address lines) dspic33fj128gp804 44 128 16 26 5 4 4 1221 3 11113 6 1/1 11 35 qfn tqfp dspic33fj128gp802 28 128 16 16 5 4 4 122131111041/0 2 21spdip soic qfn-s dspic33fj128gp204 44 128 8 26 5 4 4 122031111301/1 1135qfn tqfp dspic33fj128gp202 28 128 8 16 5 4 4 122031111001/0 2 21spdip soic qfn-s dspic33fj64gp804 4464162654 4 122131111361/1 1135qfn tqfp dspic33fj64gp802 2864161654 4 122131111041/0 2 21spdip soic qfn-s dspic33fj64gp204 4464 82654 4 122031111301/1 1135qfn tqfp dspic33fj64gp202 2864 81654 4 122031111001/0 2 21spdip soic qfn-s dspic33fj32gp304 4432 42654 4 122031111301/1 1135qfn tqfp dspic33fj32gp302 2832 41654 4 122031111001/0 2 21spdip soic qfn-s note 1: ram size is inclusive of 2 kbytes of dma ram for all devices except dspic33fj32gp302/304, which include 1 kbyte of dma ram. 2: only four out of five timers are remappable. 3: only two out of three interrupts are remappable. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 3 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 pin diagrams 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 28-pin spdip, soic av dd av ss pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 v ss v cap int0/rp7 (1) /cn23/pmd5/rb7 tdo/sda1/rp9 (1) /cn21/pmd3/rb9 tck/scl1/rp8 (1) /cn22/pmd4/rb8 an9/dac1ln/rp15 (1) /cn11/pmcs1/rb15 an10/dac1lp/rtcc/rp14 (1) /cn12/pmwr/rb14 an11/dac1rn/rp13 (1) /cn13/pmrd/rb13 an12/dac1rp/rp12 (1) /cn14/pmd0/rb12 pged2/tdi/rp10 (1) /cn16/pmd2/rb10 pgec2/tms/rp11 (1) /cn15/pmd1/rb11 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 sosco/t1ck/cn0/pma1/ra4 sosci/rp4 (1) /cn1/pmbe/rb4 osc2/clko/cn29/pma0/ra3 osc1/clki/cn30/ra2 an5/c1in+/rp3 (1) /cn7/rb3 an4/c1in-/rp2 (1) /cn6/rb2 pgec1 / an3/c2in+/rp1 (1) /cn5/rb1 pged3 / asda1/rp5 (1) /cn27/pmd7/rb5 dspic33fj64gp802 dspic33fj128gp802 28-pin spdip, soic dspic33fj32gp302 12 3 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 av dd av ss pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 v ss v cap int0/rp7 (1) /cn23/pmd5/rb7 tdo/sda1/rp9 (1) /cn21/pmd3/rb9 tck/scl1/rp8 (1) /cn22/pmd4/rb8 an9/rp15 (1) /cn11/pmcs1/rb15 an10/rtcc/rp14 (1) /cn12/pmwr/rb14 an11/rp13 (1) /cn13/pmrd/rb13 an12/rp12 (1) /cn14/pmd0/rb12 pged2/tdi/rp10 (1) /cn16/pmd2/rb10 pgec2/tms/rp11 (1) /cn15/pmd1/rb11 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 sosco/t1ck/cn0/pma1/ra4 sosci/rp4 (1) /cn1/pmbe/rb4 osc2/clko/cn29/pma0/ra3 osc1/clki/cn30/ra2 an5/c1in+/rp3 (1) /cn7/rb3 an4/c1in-/rp2 (1) /cn6/rb2 pgec1 / an3/c2in+/rp1 (1) /cn5/rb1 pged3 / asda1/rp5 (1) /cn27/pmd7/rb5 dspic33fj64gp202 dspic33fj128gp202 note 1: the rpx pins can be used by any remappab le peripheral. see tab l e 1 in this section for the list of available peripherals. = pins are up to 5v tolerant = pins are up to 5v tolerant downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 4 ? 2007-2012 microchip technology inc. pin diagrams (continued) 28-pin qfn-s (2) 23 6 1 18 19 20 21 2 2 15 7 16 17 2 3 2 4 2 5 2 6 2 7 2 8 5 4 mclr v ss v dd an0/v ref +/cn2/ra0 an1/v ref -/cn3/ra1 av dd av ss pged1/an2/c2in-/rp0 (1) /cn4/rb0 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 sosco/t1ck/cn0/pma1/ra4 sosci/rp4 (1) /cn1/pmbe/rb4 v ss osc2/clko/cn29/pma0/ra3 osc1/clki/cn30/ra2 v cap int0/rp7 (1) /cn23/pmd5/rb7 tdo/sda1/rp9 (1) /cn21/pmd3/rb9 tck/scl1/rp8 (1) /cn22/pmd4/rb8 an5/c1in+/rp3 (1) /cn7/rb3 an4/c1in-/rp2 (1) /cn6/rb2 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 an9/dac1ln/rp15 (1) /cn11/pmcs1/rb15 an10/dac1lp/rtcc/rp14 (1) /cn12/pmwr/rb14 an11/dac1rn/rp13 (1) /cn13/pmrd/rb13 an12/dac1rp/rp12 (1) /cn14/pmd0/rb12 pged2/tdi/rp10 (1) /cn16/pmd2/rb10 pgec2/tms/rp11 (1) /cn15/pmd1/rb11 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 dspic33fj64gp802 dspic33fj128gp802 14 13 12 11 10 9 8 note 1: the rpx pins can be used by any remappable peripheral. see ta b l e 1 in this section for the list of available peripherals. 2: the metal plane at the bottom of the device is not connec ted to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 5 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 pin diagrams (continued) 28-pin qfn-s (2) dspic33fj128gp202 mclr v ss v dd an0/ v ref +/cn2/ra0 an1/ v ref -/cn3/ra1 av dd av ss pged1/ an2/c2in-/rp0 (1) /cn4/rb0 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 sosco/t1ck/cn0/pma1/ra4 sosci/ rp4 (1) /cn1/pmbe/rb4 v ss osc2/clko/cn29/pma0/ra3 osc1/clki/cn30/ra2 v cap int0/rp7 (1) /cn23/pmd5/rb7 tdo/sda1/rp9 (1) /cn21/pmd3/rb9 tck/scl1/rp8 (1) /cn22/pmd4/rb8 an5/c1in+/rp3 (1) /cn7/rb3 an4/c1in-/ rp2 (1) /cn6/rb2 pgec1/ an3/c2in+/rp1 (1) /cn5/rb1 an9/dac1ln/ rp15 (1) /cn11/pmcs1/rb15 an10/dac1lp/rtcc/ rp14 (1) /cn12/pmwr/rb14 an11/ rp13 (1) /cn13/pmrd/rb13 an12/ rp12 (1) /cn14/pmd0/rb12 pged2/tdi/rp10 (1) /cn16/pmd2/rb10 pgec2/tms/rp11 (1) /cn15/pmd1/rb11 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 dspic33fj64gp202 dspic33fj32gp302 note 1: the rpx pins can be used by any remappable peripheral. see ta b l e 1 in this section for the list of available peripherals. 2: the metal plane at the bottom of the device is not conne cted to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant 23 6 1 18 19 20 21 22 15 7 16 17 23 24 25 26 27 2 8 5 4 14 13 12 11 10 9 8 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 6 ? 2007-2012 microchip technology inc. pin diagrams (continued) 44-pin qfn (2) dspic33fj64gp804 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/dac1ln/rp15 (1) /cn11/pmcs1/rb15 an10/dac1lp/rtcc/rp14 (1) /cn12/pmwr/rb14 tck/pma7/ra7 scl1/rp8 (1) /cn22/pmd4/rb8 int0/rp7 (1) /cn23/pmd5/rb7 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/pma3/rc5 rp20 (1) /cn25/pma4/rc4 rp19 (1) /cn28/pmbe/rc3 an12/dac1rp/rp12 (1) /cn14/pmd0/rb12 pgec2/rp11 (1) /cn15/pmd1/rb11 pged2/rp10 (1) /cn16/pmd2/rb10 v cap v ss rp25 (1) /cn19/pma6/rc9 rp24 (1) /cn20/pma5/rc8 rp23 (1) /cn17/pma0/rc7 rp22 (1) /cn18/pma1/rc6 sda1/rp9 (1) /cn21/pmd3/rb9 an11/dac1rn/rp13 (1) /cn13/pmrd/rb13 an4/c1in-/rp2 (1) /cn6/rb2 an5/c1in+/rp3 (1) /cn7/rb3 an6/dac1rm/rp16 (1) /cn8/rc0 an7/dac1lm/rp17 (1) /cn9/rc1 an8/cv ref /rp18 (1) /pma2/cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/pma8/ra8 dspic33fj128gp804 note 1: the rpx pins can be used by any remappable peripheral. see table 1 in this section for the list of available peripherals. 2: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 7 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 pin diagrams (continued) 44-pin qfn (2) dspic33fj64gp204 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/rp15 (1) /cn11/pmcs1/rb15 an10/rtcc/rp14 (1) /cn12/pmwr/rb14 tck/pma7/ra7 scl1/rp8 (1) /cn22/pmd4/rb8 int0/rp7 (1) /cn23/pmd5/rb7 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/pma3/rc5 rp20 (1) /cn25/pma4/rc4 rp19 (1) /cn28/pmbe/rc3 an12/rp12 (1) /cn14/pmd0/rb12 pgec2/rp11 (1) /cn15/pmd1/rb11 pged2/rp10 (1) /cn16/pmd2/rb10 v cap v ss rp25 (1) /cn19/pma6/rc9 rp24 (1) /cn20/pma5/rc8 rp23 (1) /cn17/pma0/rc7 rp22 (1) /cn18/pma1/rc6 sda1/rp9 (1) /cn21/pmd3/rb9 an11/rp13 (1) /cn13/pmrd/rb13 an4/c1in-/rp2 (1) /cn6/rb2 an5/c1in+/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/cv ref /rp18 (1) /pma2/cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/pma8/ra8 dspic33fj32gp304 dspic33fj128gp204 note 1: the rpx pins can be used by any remappable peripheral. see ta b l e 1 in this section for the list of available peripherals. 2: the metal plane at the bottom of the device is not con nected to any pins and is recommended to be connected to v ss externally. = pins are up to 5v tolerant 44 43 42 41 40 39 38 37 36 35 12 13 14 15 16 17 18 19 20 21 3 30 29 28 27 26 25 24 23 4 5 7 8 9 10 11 1 2 32 31 6 22 33 34 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 8 ? 2007-2012 microchip technology inc. pin diagrams (continued) 44-pin tqfp 10 11 2 3 4 5 61 18 19 20 21 2212 13 14 15 38 87 44 43 42 41 40 39 16 17 2930 31 32 33 2324 25 26 27 28 36 3435 9 37 scl1/rp8 (1) /cn22/pmd4/rb8 int0/rp7 (1) /cn23/pmd5/rb7 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/pma3/rc5 rp20 (1) /cn25/pma4/rc4 rp19 (1) /cn28/pmbe/rc3 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/dac1ln/rp15 (1) /cn11/pmcs1/rb15 an10/dac1lp/rtcc/rp14 (1) /cn12/pmwr/rb14 an12/dac1rp/rp12 (1) /cn14/pmd0/rb12 pgec2/rp11 (1) /cn15/pmd1/rb11 pged2/emcd2/rp10 (1) /cn16/pmd2/rb10 v cap v ss rp25 (1) /cn19/pma6/rc9 rp24 (1) /cn20/pma5/rc8 rp23 (1) /cn17/pma0/rc7 rp22 (1) /cn18/pma1/rc6 sda1/rp9 (1) /cn21/pmd3/rb9 an4/c1in-/rp2 (1) /cn6/rb2 an5/c1in+/rp3 (1) /cn7/rb3 an6/dac1rm/rp16 (1) /cn8/rc0 an7/dac1lm/rp17/ (1) /cn9/rc1 an8/cv ref /rp18 (1) /pma2/cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/pma8/ra8 an11/dac1rn/rp13 (1) /cn13/pmrd/rb13 tck/pma7/ra7 dspic33fj64gp804 dspic33fj128gp804 note 1: the rpx pins can be used by any remappable peripheral. see table 1 in this section for the list of available peripherals. = pins are up to 5v tolerant downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 9 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 pin diagrams (continued) 44-pin tqfp 10 11 2 3 4 5 61 18 19 20 21 2212 13 14 15 38 87 44 43 42 41 40 39 16 17 2930 31 32 33 2324 25 26 27 28 36 3435 9 37 scl1/rp8 (1) /cn22/pmd4/rb8 int0/rp7 (1) /cn23/pmd5/rb7 pgec3/ascl1/rp6 (1) /cn24/pmd6/rb6 pged3/asda1/rp5 (1) /cn27/pmd7/rb5 v dd tdi/pma9/ra9 sosco/t1ck/cn0/ra4 v ss rp21 (1) /cn26/pma3/rc5 rp20 (1) /cn25/pma4/rc4 rp19 (1) /cn28/pmbe/rc3 pgec1/an3/c2in+/rp1 (1) /cn5/rb1 pged1/an2/c2in-/rp0 (1) /cn4/rb0 an1/v ref -/cn3/ra1 an0/v ref +/cn2/ra0 mclr tms/pma10/ra10 av dd av ss an9/rp15 (1) /cn11/pmcs1/rb15 an10/rtcc/rp14 (1) /cn12/pmwr/rb14 an12/rp12 (1) /cn14/pmd0/rb12 pgec2/rp11 (1) /cn15/pmd1/rb11 pged2/emcd2/rp10 (1) /cn16/pmd2/rb10 v cap v ss rp25 (1) /cn19/pma6/rc9 rp24 (1) /cn20/pma5/rc8 rp23 (1) /cn17/pma0/rc7 rp22 (1) /cn18/pma1/rc6 sda1/rp9 (1) /cn21/pmd3/rb9 an4/c1in-/rp2 (1) /cn6/rb2 an5/c1in+/rp3 (1) /cn7/rb3 an6/rp16 (1) /cn8/rc0 an7/rp17 (1) /cn9/rc1 an8/cv ref /rp18 (1) /pma2/cn10/rc2 sosci/rp4 (1) /cn1/rb4 v dd v ss osc1/clki/cn30/ra2 osc2/clko/cn29/ra3 tdo/pma8/ra8 an11/rp13 (1) /cn13/pmrd/rb13 tck/pma7/ra7 dspic33fj32gp304 dspic33fj64gp204 dspic33fj128gp204 note 1: the rpx pins can be used by any remappable peripheral. see ta b l e 1 in this section for the list of available peripherals. = pins are up to 5v tolerant downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 10 ? 2007-2012 microchip technology inc. table of contents dspic33fj32gp302/304, dspic33fj 64gpx02/x04, and dspic33fj128gpx 02/x04 product families............................................. 2 1.0 device overview ........................................................................................................................................................................ 13 2.0 guidelines for getting started with 16 -bit digital signal controllers ....................................................... ................................... 19 3.0 cpu............................................................................................................................................................................................ 23 4.0 memory organization ......................................................................................................... ........................................................ 35 5.0 flash program memory ........................................................................................................ ...................................................... 71 6.0 resets ..................................................................................................................... .................................................................. 77 7.0 interrupt controller ..................................................................................................................................................................... 87 8.0 direct memory access (dma) .................................................................................................. ................................................ 129 9.0 oscillator configuration ............................................................................................................................................................ 141 10.0 power-saving features............................................................................................................................................................ 153 11.0 i/o ports ................................................................................................................................................................................... 159 12.0 timer1 ...................................................................................................................................................................................... 189 13.0 timer2/3 and timer4/5 feature ............................................................................................................................................... 193 14.0 input capture............................................................................................................................................................................ 199 15.0 output compare....................................................................................................................................................................... 203 16.0 serial peripheral interface (spi).......................................................................................... ..................................................... 207 17.0 inter-integrated circuit? (i 2 c?) .............................................................................................................................................. 213 18.0 universal asynchronous rece iver transmitter (uart) ........................................................................................................... 221 19.0 enhanced can (ecan?) module ................................................................................................ ........................................... 227 20.0 data converter interface (dci) module...................................................................................... .............................................. 255 21.0 10-bit/12-bit analog-to-digital converter (adc) ............................................................................ ........................................... 263 22.0 audio digital-to-analog converter (dac) .................................................................................... ............................................. 277 23.0 comparator module.................................................................................................................................................................. 283 24.0 real-time clock and calendar (rtcc) .................................................................................................................................. 289 25.0 programmable cyclic redundancy check (crc) generator ....................................................................... ........................... 301 26.0 parallel master port (pmp)................................................................................................. ...................................................... 307 27.0 special features ...................................................................................................................................................................... 315 28.0 instruction set summary .......................................................................................................................................................... 325 29.0 development support............................................................................................................................................................... 333 30.0 electrical characteristics .......................................................................................................................................................... 337 31.0 high temperature electrical characteristics ............................................................................................................................ 391 32.0 dc and ac device characteristics graphs.............................................................................................................................. 403 33.0 packaging information.............................................................................................................................................................. 407 appendix a: revision history............................................................................................................................................................. 417 index .................................................................................................................................................................................................. 4 27 the microchip web site ......................................................................................................... ............................................................ 431 customer change notification service .............................................................................................................................................. 431 customer support .............................................................................................................................................................................. 431 reader response ................................................................................................................ .............................................................. 432 product identification system.................................................................................................. ........................................................... 433 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 11 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicat ions to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regard ing this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documen tation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and dat a sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 12 ? 2007-2012 microchip technology inc. referenced sources this device data sheet is based on the following individual chapters of the dspic33f/pic24h family reference manual . these documents should be considered as the general re ference for the operation of a particular module or device feature. section 1. introduction (ds70197) section 2. cpu (ds70204) section 3. data memory (ds70202) section 4. program memory (ds70203) section 5. flash programming (ds70191) section 8. reset (ds70192) section 9. watchdog timer and power-saving modes (ds70196) section 11. timers (ds70205) section 12. input capture (ds70198) section 13. output compare (ds70209) section 16. analog-to-digital converter (adc) (ds70183) section 17. uart (ds70188) section 18. serial peri pheral interface (spi) (ds70206) section 19. inter-integrated circuit? (i 2 c?) (ds70195) section 23. codeguard? security (ds70199) section 24. programming and diagnostics (ds70207) section 25. device configuration (ds70194) section 30. i/o ports with peripheral pin select (pps) (ds70190) section 32. interrupts (part iii) (ds70214) section 33. audio digital-to-analog converter (dac) (ds70211) section 34. comparator (ds70212) section 35. parallel master port (pmp) (ds70299) section 36. programmable cyclic redundancy check (crc) (ds70298) section 37. real-time clock and calendar (rtcc) (ds70301) section 38. direct memory access (dma) (part iii) (ds70215) section 39. oscillator (part iii) (ds70216) note 1: to access the documents listed below, browse to the documentation section of the dspic33fj64gp804 product page of the microchip web site ( www.microchip.com ) or select a family reference manual section from the following list. in addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 13 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 1.0 device overview this document contains device specific information for the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 digital signal controller (dsc) devices. the dspic33f devices contain extensive digital signal processor (dsp) functionality with a high performance 16-bit microcontroller (mcu) architecture. figure 1-1 shows a general block diagram of the core and peripheral modules in the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to the dspic33f/pic24h family reference manual . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 14 ? 2007-2012 microchip technology inc. figure 1-1: dspic33fj32gp302/304, dspic 33fj64gpx02/x04, and dspic33fj128gpx02/ x04 block diagram 16 osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap ic1, 2, 7, 8 i2c1 porta note: not all pins or features are implemented on all device pinout c onfigurations. see pinout diagrams for the specific pins and fea tures present on each device. instruction decode and control pch pcl 16 program counter 16-bit alu 23 23 24 23 instruction reg pcu 16 x 16 w register array rom latch 16 ea mux 16 16 8 interrupt controller psv and table data access control block stack control logic loop control logic data latch address latch address latch program memory data latch literal data 16 16 16 16 data latch address latch 16 x ram y ram 16 y data bus x data bus dsp engine divide support 16 control signals to various blocks adc1 timers portb address generator units 1-5 cnx uart1, 2 oc/ pwm1-4 dci remappable pins dmaram dma controller portc spi1, 2 ecan1 dac1 comparator 2 ch. rtcc pmp/ epsp downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 15 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 1-1: pinout i/o descriptions pin name pin type buffer type pps description an0-an12 i analog analog input channels. clki clko i o st/cmos nono external clock source input. al ways associated with osc1 pin function. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with osc2 pin function. osc1osc2 i i/o st/cmos nono oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. optionally functions as clko in rc and ec modes. soscisosco i o st/cmos nono 32.768 khz low-power oscillator crystal input; cmos otherwise. 32.768 khz low-power oscillator crystal output. cn0-cn30 i st no no change notification inputs. can be software programmed for internal weak pull-ups on all inputs. ic1-ic2ic7-ic8 ii stst yes yes capture inputs 1/2. capture inputs 7/8. ocfa oc1-oc4 i o st yes yes compare fault a input (for compare channels 1, 2, 3 and 4). compare outputs 1 through 4. int0 int1 int2 ii i stst st no yes yes external interrupt 0. external interrupt 1. external interrupt 2. ra0-ra4 ra7-ra10 i/o i/o stst nono porta is a bidirectional i/o port. porta is a bidirectional i/o port. rb0-rb15 i/o st no portb is a bidirectional i/o port. rc0-rc9 i/o st no portc is a bidirectional i/o port. t1ck t2ck t3ck t4ck t5ck ii i i i stst st stst no yes yes yes yes timer1 external clock input. timer2 external clock input. timer3 external clock input. timer4 external clock input. timer5 external clock input. u1cts u1rts u1rx u1tx i o i o st st yes yes yes yes uart1 clear to send. uart1 ready to send. uart1 receive. uart1 transmit. u2cts u2rts u2rx u2tx i o i o st st yes yes yes yes uart2 clear to send. uart2 ready to send. uart2 receive. uart2 transmit. sck1sdi1 sdo1 ss1 i/o i o i/o stst st yes yes yes yes synchronous serial clock input/output for spi1. spi1 data in. spi1 data out. spi1 slave synchronization or frame pulse i/o. sck2sdi2 sdo2 ss 2 i/o i o i/o stst st yes yes yes yes synchronous serial clock input/output for spi2. spi2 data in. spi2 data out. spi2 slave synchronization or frame pulse i/o. legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 16 ? 2007-2012 microchip technology inc. scl1sda1 ascl1 asda1 i/o i/o i/o i/o stst st st nono no no synchronous serial clock input/output for i2c1. synchronous serial data input/output for i2c1. alternate synchronous serial clock input/ output for i2c1. alternate synchronous serial data input/output for i2c1. tms tck tdi tdo ii i o stst st nono no no jtag test mode select pin. jtag test clock input pin. jtag test data input pin. jtag test data output pin. c1rx c1tx i o st yes yes ecan1 bus receive pin. ecan1 bus transmit pin. rtcc o no real-time clock alarm output. cv ref o ana no comparator voltage reference output. c1in- c1in+ c1out ii o anaana nono yes comparator 1 negative input. comparator 1 positive input. comparator 1 output. c2in- c2in+ c2out ii o anaana nono yes comparator 2 negative input. comparator 2 positive input. comparator 2 output. pma0 pma1 pma2 -pmpa10 pmbe pmcs1 pmd0-pmpd7 pmrd pmwr i/o i/o oo o i/o oo ttl/st ttl/st ttl/st nono no no no no no no parallel master port address bit 0 input (buffered slave modes) and output (master modes). parallel master port address bit 1 input (buffered slave modes) and output (master modes). parallel master port address (demultiplexed master modes). parallel master port byte enable strobe. parallel master port chip select 1 strobe. parallel master port data (demultiplexed master mode) or address/ data (multiplexed master modes). parallel master po rt read strobe. parallel master port write strobe. dac1rn dac1rp dac1rm oo o nono no dac1 right channel negative output. dac1 right channel positive output. dac1 right channel middle point value (typically 1.65v). dac1ln dac1lp dac1lm oo o nono no dac1 left channel negative output. dac1 left channel positive output. dac1 left channel middle point value (typically 1.65v). cofs i/o st yes data converter interface frame synchronization pin. csck i/o st yes data converter interfac e serial clock input/output pin. csdi i st yes data converter interface serial data input pin csdo o yes data converter interface serial data output pin. pged1 pgec1 pged2 pgec2 pged3 pgec3 i/o i i/o i i/o i stst st st st st nono no no no no data i/o pin for programming/debugging communication channel 1. clock input pin for programming/debugging communication channel 1. data i/o pin for programming/debugging communication channel 2. clock input pin for programming/debugging communication channel 2. data i/o pin for programming/debugging communication channel 3. clock input pin for programming/debugging communication channel 3. mclr i/p st no master clear (reset) input. this pin is an active-low reset to the device. av dd p p no positive supply for analog modules. this pin must be connected at all times. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 17 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 av ss p p no ground reference for analog modules. v dd p no positive supply for peripheral logic and i/o pins. v cap p no cpu logic filter capacitor connection. vss p no ground reference for logic and i/o pins. v ref + i analog no analog voltage reference (high) input. v ref - i analog no analog voltage reference (low) input. table 1-1: pinout i/o descriptions (continued) pin name pin type buffer type pps description legend: cmos = cmos compatible input or output analog = analog input p = power st = schmitt trigger input with cmos levels o = output i = input ttl = ttl input buffer pps = peripheral pin select downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 18 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 19 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 2.0 guidelines for getting started with 16-bit digital signal controllers 2.1 basic connection requirements getting started with th e dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 family of 16-bit digital signal controllers (dscs) requires attention to a minimal set of device pin connections before proceeding with development. the following is a list of pin names, which must always be connected: all v dd and v ss pins (see section 2.2 decoupling capacitors ) all av dd and av ss pins (regardless if adc module is not used) (see section 2.2 decoupling capacitors ) v cap (see section 2.3 cpu logic filter capacitor connection (v cap ) ) mclr pin (see section 2.4 master clear (mclr) pin ) pgecx/pgedx pins used for in-circuit serial programming? (icsp?) and debugging purposes (see section 2.5 icsp pins ) osc1 and osc2 pins when external oscillator source is used (see section 2.6 externa l oscillator pins ) additionally, the following pins may be required: v ref +/v ref - pins used when external voltage reference for adc module is implemented 2.2 decoupling capacitors the use of decoupling capacitors on every pair of power supply pins, such as v dd , v ss , av dd and av ss is required. consider the following criteria when using decoupling capacitors: value and type of capacitor: recommendation of 0.1 f (100 nf), 10-20v. this capacitor should be a low-esr and have resonance frequency in the range of 20 mhz and higher. it is recommended that ceramic capacitors be used. placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended to place the capacitors on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the primary decoupling capacitor. in high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decoupling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: the av dd and av ss pins must be connected independent of the adc voltage reference source. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 20 ? 2007-2012 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 tank capacitors on boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including dscs to supply a local power source. the value of the tank capacitor should be determined based on the trace resistance that con- nects the power supply sour ce to the device, and the maximum current drawn by the device in the applica- tion. in other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. typical values range from 4.7 f to 47 f. 2.3 cpu logic filter capacitor connection (v cap ) a low-esr (< 5 ohms) capacitor is required on the v cap pin, which is used to stabilize the voltage regulator output voltage. the v cap pin must not be connected to v dd , and must have a capacitor between 4.7 f and 10 f, preferably surface mount connected within one-eights inch of the v cap pin connected to ground. the type can be ceramic or tantalum. refer to section 30.0 electrical characteristics for additional information. the placement of this capacitor should be close to the v cap . it is recommended that the trace length not exceed one-quarter inch (6 mm). refer to section 27.2 on-chip voltage regulator for details. 2.4 master clear (mclr ) pin the mclr pin provides for two specific device functions: device reset device programming and debugging during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adve rsely affected. therefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as shown in figure 2-2 , it is recommended that the capaci tor c, be isolated from the mclr pin during programming and debugging operations. place the components shown in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections dspic33f v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic v cap l1 (1) r1 10 f tantalum note 1: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 and the inductor capacity greater than 10 ma. where: f f cnv 2 ------------- - = f 1 2 lc () ----------------------- = l 1 2 fc () --------------------- ?? ?? 2 = (i.e., adc conversion rate/2) note 1: r 10 k is recommended. a suggested starting value is 10 k . ensure that the mclr pin v ih and v il specifications are met. 2: r1 470 will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. c r1 (2) r (1) v dd mclr dspic33f jp downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 21 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur- poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes, and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi- cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the communication channel select (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? icd 3 or mplab real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are availabl e on the microchip website. using mplab ? icd 3 in-circuit debugger (poster) ds51765 mplab ? icd 3 design advisory ds51764 mplab ? real ice? in-circuit emulator users guide ds51616 using mplab ? real ice? (poster) ds51749 2.6 external oscillator pins many dscs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 9.0 oscillator configuration for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator circuit close to t he respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or power traces inside the ground pour. also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. a suggested layout is shown in figure 2-3 . recommendations for crystals and ceramic resonators are provided in table 2-1 and ta b l e 2 - 2 , respectively. figure 2-3: suggested placement of the oscillator circuit table 2-1: crystal recommendations 13 main oscillator guard ring guard trace secondary oscillator 14 15 16 17 18 19 20 part number vendor freq. load cap. package case frequency tolerance mounting type operating temperature ecs-40-20-4dn ecs inc. 4 mhz 20 pf hc49/us 30 ppm th -40c to +85c ecs-80-18-4dn ecs inc. 8 mhz 18 pf hc49/us 30 ppm th -40c to +85c ecs-100-18-4-dn ecs inc. 10 mhz 18 pf hc49/us 30 ppm th -40c to +85c ecs-200-20-4dn ecs inc. 20 mhz 20 pf hc49/us 30 ppm th -40c to +85c ecs-40-20-5g3xds-tr ecs inc. 4 mhz 20 pf hc49/us 30 ppm sm -40c to +125c ecs-80-20-5g3xds-tr ecs inc. 8 mhz 20 pf hc49/us 30 ppm sm -40c to +125c ecs-100-20-5g3xds-tr ecs inc. 10 mhz 20 pf hc49/us 30 ppm sm -40c to +125c ecs-200-20-5g3xds-tr ecs inc. 20 mhz 20 pf hc49/us 30 ppm sm -40c to 125c nx3225sa 20mhz at-w ndk 20 mhz 8 pf 3.2 mm x 2.5 mm 50 ppm sm -40c to 125c legend: th = through hole sm = surface mount downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 22 ? 2007-2012 microchip technology inc. table 2-2: resonator recommendations 2.7 oscillator value conditions on device start-up if the pll of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 8 mhz for start-up with the pll enabled to comply with device pll start-up cond itions. this means that if the external oscillator frequency is outside this range, the application must start-up in the frc mode first. the default pll settings after a por with an oscillator frequency outside this range will violate the device operating speed. once the device powers up, the application firmware can initialize the pll sfrs, clkdiv and plldbf to a suitable value, and then perform a clock switch to the oscillator + pll clock source . note that clock switching must be enabled in the device configuration word. 2.8 configuration of analog and digital pins during icsp operations if mplab icd 3 or real ice is selected as a debug- ger, it automatically initializes all of the analog-to-digital input pins (anx) as digital pins, by setting all bits in the ad1pcfgl register. the bits in this register that correspond to the analog-to-digital pins that are initialized by mplab icd 3 or real ice, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. if your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ad1pcfgl register during initialization of the adc module. when mplab icd 3 or real ice is used as a programmer, the user application firmware must correctly configure the ad1p cfgl register . automatic initialization of this register is only done during debugger operation. failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic 0 , which may affect user application functionality. 2.9 unused i/os unused i/o pins should be configured as outputs and driven to a logic-low state. alternatively, connect a 1k to 10k resistor between v ss and the unused pin. part number vendor freq. load cap. package case frequency tolerance mounting type operating temperature fcr4.0m5t tdk corp. 4 mhz n/a ra dial 0.5% th -40c to +85c fcr8.0m5 tdk corp. 8 mhz n/a radial 0.5% th -40c to +85c hwzt-10.00md tdk corp. 10 mhz n/a radial 0.5% th -40c to +85c hwzt-20.00md tdk corp. 20 mhz n/a radial 0.5% th -40c to +85c legend: th = through hole downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 23 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 3.0 cpu 3.1 overview the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 cpu module has a 16-bit (data) modified harvard architecture with an enhanced instruction set, in cluding significant support for dsp. the cpu has a 24-bit instruction word with a variable length opcode field. the program counter (pc) is 23 bits wide and addresses up to 4m x 24 bits of user program memory sp ace. the actual amount of program memory implemented varies by device. a single-cycle instruction pref etch mechanism is used to help maintain throughput and provides predictable execution. all instructions execute in a single cycle, with the exception of instru ctions that change the program flow, the double-word move ( mov.d ) instruction and the table instructions. overhead-free program loop constructs are supported using the do and repeat instructions, both of which are interruptible at any time. the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 devices have sixteen, 16-bit working registers in the programmers model. each of the working registers can serve as a data, address or address offset register. the 16th working register (w15) operates as a software stack pointer (sp) for interrupts and calls. there are two classes of instruction in the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices: mcu and dsp. these two instructio n classes are seamlessly integrated into a single cpu. the instruction set includes many addressing modes and is designed for optimum c compiler efficiency. for most instructions, the dspic33fj32gp302/ 304, dspic33fj64gpx02/ x04, and dspic33fj128g px02/x04 is capable of executing a data (or program data) memory read, a working register (data) read , a data memory write and a program (instruction) memory read per instruction cycle. as a result, three parameter instructions can be supported, allowing a + b = c operations to be executed in a single cycle. a block diagram of the cpu is shown in figure 3-1 , and the programmers model for the dspic33fj32gp302/ 304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 is shown in figure 3-2 . 3.2 data addressing overview the data space can be addressed as 32k words or 64 kbytes and is split into two blocks, referred to as x and y data memory. each memory block has its own independent address generation unit (agu). the mcu class of instructions operates solely through the x memory agu, which accesses the entire memory map as one linear data space. certain dsp instructions operate through the x and y agus to support dual operand reads, which splits the data address space into two parts. the x and y data space boundary is device-specific. overhead-free circular buffers (modulo addressing mode) are supported in both x and y address spaces. the modulo addressing removes the software boundary checking overhead for dsp algorithms. furthermore, the x agu circular addressing can be used with any of the mcu class of instructions. the x agu also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 fft algorithms. the upper 32 kbytes of the data space memory map can optionally be mapped into program space at any 16k program word boundary defined by the 8-bit program space visibility page (psvpag) register. the program-to-data-space mapping feature lets any instruction access program space as if it were data space. 3.3 dsp engine overview the dsp engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit alu, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. the barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. the dsp instructions operate seamlessly with all other instructions and have been designed for optimal real- time performance. the mac instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two w registers and accumulating and optionally saturating the result in the same cycle. this instruction functionality requires that the ram data space be split for these instructions and linear for all others. data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 2. cpu (ds70204) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 24 ? 2007-2012 microchip technology inc. 3.4 special mcu features the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 features a 17-bit by 17-bit single-cycle multip lier that is shared by both the mcu alu and dsp engine. the multiplier can per- form signed, unsigned and mixed-sign multiplication. using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achi eves accurate results for special operations, such as (-1.0) x (-1.0). the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128g px02/x04 supports 16/16 and 32/16 divide operations, both fractional and inte- ger. all divide instructions are iterative operations. they must be executed within a repeat loop, resulting in a total execution time of 19 instruction cycles. the divide operation can be interrupt ed during any of those 19 cycles without loss of data. a 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a sing le cycle. the barrel shifter can be used by both mcu and dsp instructions. figure 3-1: dspic33fj32gp302/304, dspic 33fj64gpx02/x04, and dspic33fj128gpx02/ x04 cpu core block diagram instruction decode and control pch pcl program counter 16-bit alu 24 23 instruction reg pcu 16 x 16 w register array rom latch ea mux interrupt controller stack control logic loop control logic data latch address latch control signals to various blocks literal data 16 16 16 to peripheral modules data latch address latch 16 x ram y ram address generator units 16 y data bus x data bus dma controller dmaram dsp engine divide support 16 16 23 23 16 8 psv and table data access control block 16 16 16 16 program memory data latch address latch downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 25 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 3-2: dspic33fj32gp302/304, dspi c33fj64gpx02/x04, and dspic33fj128gpx02/ x04 programmers model pc22 pc0 7 0 d0 d15 program counter data table page address status register working registers dsp operand registers w1w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12/dsp offset w13/dsp write back w14/frame pointer w15/stack pointer dsp address registers ad39 ad0 ad31 dsp accumulators accaaccb 7 0 program space visibi lity page address z 0 oa ob sa sb rcount 15 0 repeat loop counter dcount 15 0 do loop counter dostart 22 0 do loop start address ipl2 ipl1 splim stack pointer limit register ad15 srl push.s shadow do shadow oab sab 15 0 core configuration register legend corcon da dc ra n tblpag psvpag ipl0 ov w0/wreg srh do loop end address doend 22 c downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 26 ? 2007-2012 microchip technology inc. 3.5 cpu resources many useful resources are provided on the main prod- uct page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 3.5.1 key resources section 2. cpu (ds70204) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 27 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 3.6 cpu control registers register 3-1: sr: cpu status register r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r -0 r/w-0 oa ob sa (1) sb (1) oab sab (4) da dc bit 15 bit 8 r/w-0 (3) r/w-0 (3) r/w-0 (3) r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> (2) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as 0 s = set only bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 oa: accumulator a overflow status bit 1 = accumulator a overflowed 0 = accumulator a has not overflowed bit 14 ob: accumulator b overflow status bit 1 = accumulator b overflowed 0 = accumulator b has not overflowed bit 13 sa: accumulator a saturation sticky status bit (1) 1 = accumulator a is saturated or has been saturated at some time 0 = accumulator a is not saturated bit 12 sb: accumulator b saturation sticky status bit (1) 1 = accumulator b is saturated or has been saturated at some time 0 = accumulator b is not saturated bit 11 oab: oa || ob combined accumu lator overflow status bit 1 = accumulators a or b have overflowed 0 = neither accumulators a or b have overflowed bit 10 sab: sa || sb combined accumulator (sticky) status bit (4) 1 = accumulators a or b are saturated or hav e been saturated at some time in the past 0 = neither accumulator a or b are saturated bit 9 da: do loop active bit 1 = do loop in progress 0 = do loop not in progress bit 8 dc: mcu alu half carry/borrow bit 1 = a carry-out from the 4th low-order bit (for byte-s ized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = no carry-out from the 4th low-order bit (for by te-sized data) or 8th low- order bit (for word-sized data) of the result occurred note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read only when the nstdis bit (intcon1<15>) = 1 . 4: this bit can be read or cleared (not set). clearing this bit clears sa and sb. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 28 ? 2007-2012 microchip technology inc. bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15), user interrupts disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) bit 4 ra: repeat loop active bit 1 = repeat loop in progress 0 = repeat loop not in progress bit 3 n: mcu alu negative bit 1 = result was negative 0 = result was non-negative (zero or positive) bit 2 ov: mcu alu overflow bit this bit is used for signed arithmetic (twos comp lement). it indicates an overflow of a magnitude that causes the sign bit to change state. 1 = overflow occurred for signed arit hmetic (in this arithmetic operation) 0 = no overflow occurred bit 1 z: mcu alu zero bit 1 = an operation that affects the z bit has set it at some time in the past 0 = the most recent operation that affects the z bit has cleared it (i.e., a non-zero result) bit 0 c: mcu alu carry/borrow bit 1 = a carry-out from the most sign ificant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred register 3-1: sr: cpu status register (continued) note 1: this bit can be read or cleared (not set). 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read only when the nstdis bit (intcon1<15>) = 1 . 4: this bit can be read or cleared (not set). clearing this bit clears sa and sb. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 29 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 3-2: corcon: core control register u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 u se d t (1) dl<2:0> bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 (2) psv rnd if bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown u = unimplemented bit, read as 0 bit 15-13 unimplemented: read as 0 bit 12 us: dsp multiply unsigned/signed control bit 1 = dsp engine multiplies are unsigned 0 = dsp engine multiplies are signed bit 11 edt: early do loop termination control bit (1) 1 = terminate executing do loop at end of current loop iteration 0 = no effect bit 10-8 dl<2:0>: do loop nesting level status bits 111 = 7 do loops active 001 = 1 do loop active 000 = 0 do loops active bit 7 sata: acca saturation enable bit 1 = accumulator a saturation enabled 0 = accumulator a saturation disabled bit 6 satb: accb saturation enable bit 1 = accumulator b saturation enabled 0 = accumulator b saturation disabled bit 5 satdw: data space write from dsp engine saturation enable bit 1 = data space write saturation enabled 0 = data space write saturation disabled bit 4 accsat: accumulator saturation mode select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less bit 2 psv: program space visibility in data space enable bit 1 = program space visible in data space 0 = program space not visible in data space bit 1 rnd: rounding mode select bit 1 = biased (conventional) rounding enabled 0 = unbiased (convergent) rounding enabled bit 0 if: integer or fractional multiplier mode select bit 1 = integer mode enabled for dsp multiply ops 0 = fractional mode enabled for dsp multiply ops note 1: this bit is always read as 0 . 2: the ipl3 bit is concatenated with the ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 30 ? 2007-2012 microchip technology inc. 3.7 arithmetic logic unit (alu) the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 alu is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. un less otherwise mentioned, arithmetic operati ons are twos complement in nature. depending on the operation, the alu can affect the values of the carry (c), zero (z), negative (n), overflow (ov) and digit carry (dc) status bits in the sr register. the c and dc status bits operate as borrow and digit borrow bits, respectively, for subtraction operations. the alu can perform 8-bit or 16-bit operations, depending on the mode of t he instruction that is used. data for the alu operation can come from the w register array or data memory, depending on the addressing mode of the instruction. likewise, output data from the alu can be writte n to the w register array or a data memory location. refer to the 16-bit mcu and dsc programmers ref- erence manual (ds70157) for information on the sr bits affected by each instruction. the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 cpu incorpo- rates hardware support for both multiplication and divi- sion. this includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.7.1 multiplier using the high-speed 17-bit x 17-bit multiplier of the dsp engine, the alu supports unsigned, signed or mixed-sign operation in several mcu multiplication modes: 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.7.2 divider the divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide the quotient for all divide instructions ends up in w0 and the remainder in w1. 16-bit signed and unsigned div instructions can specif y any w register for both the 16-bit divisor (wn) and any w register (aligned) pair (w(m + 1):wm) for the 32-bit dividend. the divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16- bit instructi ons take the same number of cycles to execute. 3.8 dsp engine the dsp engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic3 3fj128gpx02/x04 is a single-cycle instruction flow architectu re; therefore, concurrent operation of the dsp engine with mcu instruction flow is not possible. however, some mcu alu and dsp engine resources can be used concurrently by the same instruction (e.g., ed, edac). the dsp engine can also perform inherent accumula- tor-to-accumulator operations that require no additional data. these instructions are add, sub and neg . the dsp engine has options selected through bits in the cpu core control register (corcon), as listed below: fractional or integer dsp multiply (if) signed or unsigned dsp multiply (us) conventional or convergent rounding (rnd) automatic saturation on/off for acca (sata) automatic saturation on/off for accb (satb) automatic saturation on/off for writes to data memory (satdw) accumulator saturation mode selection (acc- sat) a block diagram of the dsp engine is shown in figure 3-3 . table 3-1: dsp instructions summary instruction algebraic operation acc write back clr a = 0 yes ed a = (x C y) 2 no edac a = a + (x C y) 2 no mac a = a + (x y) yes mac a = a + x2 no movsac no change in a yes mpy a = x y no mpy a = x 2 no mpy.n a = C x y no msc a = a C x y yes downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 31 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 3-3: dsp engine block diagram zero backfill sign-extend barrel shifter 40-bit accumulator a 40-bit accumulator b round logic x data bus to/from w array adder saturate negate 32 32 33 16 16 16 16 40 40 40 40 s a t u r a t e y data bus 40 carry/borrow out carry/borrow in 16 40 multiplier/scaler 17-bit downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 32 ? 2007-2012 microchip technology inc. 3.8.1 multiplier the 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (q31) or 32-bit integer results. unsigned operands are zero-extended into the 17th bit of the multiplier input value. signed operands are sign-extended into the 17th bit of the multiplier input value. the ou tput of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. integer data is inherently represented as a signed twos complement value, where the most significant bit (msb) is defined as a sign bit. the range of an n-bit twos complement integer is -2 n-1 to 2 n-1 C 1. for a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7fff) including 0. for a 32-bit integer, the data range is - 2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7fff ffff). when the multiplier is configured for fractional multiplication, the data is represented as a twos complement fraction, where the msb is defined as a sign bit and the radix point is implied to lie just after the sign bit (qx format). the range of an n-bit twos complement fraction with this implied radix point is -1.0 to (1 C 2 1-n ). for a 16-bit fraction, the q15 data range is -1.0 (0x8000) to 0.999969482 (0x7fff) including 0 and has a precision of 3.01518x10 -5 . in fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a pr ecision of 4.65661 x 10 -10 . the same multiplier is used to support the mcu multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. the mul instruction can be directed to use byte or word-sized operands. byte operands direct a 16-bit result, and word operands direct a 32-bit result to the specified registers in the w array. 3.8.2 data accumulators and adder/subtracter the data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. it can select one of two accumulators (a or b) as its pre- accumulation source and post-accumulation destination. for the add and lac instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.8.2.1 adder/subtracter, overflow and saturation the adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. in the case of addition, the carry/b orrow input is active-high and the other input is true data (not complemented). in the case of subtraction, the carry/borrow input is active-low and the other input is complemented. the adder/subtracter generates overflow status bits, sa/sb and oa/ob, which are latched and reflected in the status register: overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. overflow into guard bits 32 through 39: this is a recoverable overflow. this bit is set whenever all the guard bits are not identical to each other. the adder has an additional saturation block that controls accumulator data saturation, if selected. it uses the result of the adder, the overflow status bits described previously and the sat ? 2007-2012 microchip tec hnology inc. ds70292g-page 33 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 the overflow and saturation status bits can optionally be viewed in the status register (sr) as the logical or of oa and ob (in bit oab) and the logical or of sa and sb (in bit sab). programmers can check one bit in the status register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. this is useful for complex number arithmetic, which typically uses both accumulators. the device supports three saturation and overflow modes: bit 39 overflow and saturation: when bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7fffffffff) or maximally negative 9.31 value (0x8000000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. this condition is referred to as super saturation and pr ovides protection against erroneous data or unexpected algorithm problems (such as gain calculations). bit 31 overflow and saturation: when bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007fffffff) or maximally nega- tive 1.31 value (0x0080000000) into the target accumulator. the sa or sb bit is set and remains set until cleared by the user application. when this saturation mode is in effect, the guard bits are not used, so the oa, ob or oab bits are never set. bit 39 catastrophic overflow: the bit 39 overflow status bit from the adder is used to set the sa or sb bit, which remains set until cleared by the user application. no saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. if the covte bit in the intcon1 register is set, a catastrophic overflow can initiate a trap exception. 3.8.3 accumulator write back the mac class of instructions (with the exception of mpy, mpy.n, ed and edac ) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is no t targeted by the instruction into data space memory. the write is performed across the x bus into combined x and y address space. the following addressing modes are supported: w13, register direct: the rounded contents of the non-target accumulator are written into w13 as a 1.15 fraction. [w13] + = 2, register i ndirect with post-increment: the rounded contents of t he non-target accumu- lator are written into the address pointed to by w13 as a 1.15 fraction. w13 is then incremented by 2 (for a word write). 3.8.3.1 round logic the round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). the round mode is determined by the state of the rnd bit in the corcon register. it generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. if rounding is not indicated by the instruction, a truncated 1. 15 data value is stored and the least significant word is simply discarded. conventional rounding zero-extends bit 15 of the accu- mulator and adds it to the accxh word (bits 16 through 31 of the accumulator). if the accxl word (bits 0 through 15 of the accu- mulator) is between 0x8000 and 0xffff (0x8000 included), accxh is incremented. if accxl is between 0x0000 and 0x7fff, accxh is left unchanged. a consequence of this algorithm is that over a succes- sion of random rounding operations, the value tends to be biased slightly positive. convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when accxl equals 0x8000. in this case, the least significant bit (bit 16 of t he accumulator) of accxh is examined: if it is 1 , accxh is incremented. if it is 0 , accxh is not modified. assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. the sac and sac.r instructions store either a truncated ( sac ), or rounded ( sac.r ) version of the contents of the target accumulator to data memory via the x bus, subject to data saturation (see section 3.8.3.2 data space write saturation ). for the mac class of instructions, the accumulator write- back operation functions in the same manner, addressing combined mcu (x and y) data space though the x bus. for this class of instructions, the data is always subject to rounding. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 34 ? 2007-2012 microchip technology inc. 3.8.3.2 data space write saturation in addition to adder/subtracter saturation, writes to data space can also be saturat ed, but without affecting the contents of the source accumulator. the data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. these inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. if the satdw bit in the corcon register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: for input data greater than 0x007fff, data written to memory is forced to the maximum positive 1.15 value, 0x7fff. for input data less than 0xff8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. the most significant bit of t he source (bit 39) is used to determine the sign of the operand being tested. if the satdw bit in the corco n register is not set, the input data is always passed through unmodified under all conditions. 3.8.4 barrel shifter the barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. the source can be either of the two dsp accumulators or the x bus (to support multi-bit shifts of register or memory data). the shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. a positive value shifts the operand right. a negative value shifts the operand left. a value of 0 does not modify the operand. the barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for dsp shift operations and a 16-bit result for mcu shift operations. data from the x bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 35 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.0 memory organization the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128g px02/x04 architecture features separate program and data memory spaces and buses. this architecture also allows the direct access of program memory from the data space during code execution. 4.1 program address space the program address memory space of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices is 4m instructions. the space is addressable by a 24-bit value derived either from the 23-bit program counter (pc) during program executi on, or from table operation or data space remapping as described in section 4.8 interfacing program and data memory spaces . user application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7fffff). the exception is the use of tblrd/tblwt operations, which use tblpag<7> to permit access to the configuration bits and device id sections of the configuration memory space. the memory map for the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices is shown in figure 4-1 . figure 4-1: program memory map for ds pic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj1 28gpx02/x04 devices note: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. program memory (ds70203) of the dspic33f/ pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). reset address 0x000000 0x0000fe 0x000002 0x000100 device configuration user program flash memory (11264 instructions) 0x800000 0xf80000 registers 0xf80017 0xf80018 devid (2) 0xfefffe0xff0000 0xff0002 0xf7fffe unimplemented (read 0 s) goto instruction 0x000004 reserved 0x7ffffe reserved 0x000200 0x0001fe 0x000104 alternate vector table reserved interrupt vector table dspic33fj32gp302/304 configuration memory space user memory space note: memory areas are not shown to scale. reset address device configuration user program flash memory (22016 instructions) registers devid (2) unimplemented (read 0 s) goto instruction reserved reserved alternate vector table reserved interrupt vector table dspic33fj64gpx02/x04 reset address device configuration user program flash memory (44032 instructions) registers devid (2) unimplemented (read 0 s) goto instruction reserved reserved alternate vector table reserved interrupt vector table dspic33fj128gpx02/x04 0x0057fe 0x005800 0x015800 0x0157fe 0x00ac00 0x00abfe reserved reserved reserved 0xfffffe downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 36 ? 2007-2012 microchip technology inc. 4.1.1 program memory organization the program memory space is organized in word- addressable blocks. although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. the lower word always has an even address, while the upper word has an odd address ( figure 4-2 ). program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. this arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. 4.1.2 interrupt and trap vectors all dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. a hardware reset vector is provided to redirect code execution from the default value of the pc on device reset to the actual start of code. a goto instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000ff and 0x000100 to 0x0001ff. these vector tables allow each of the device interrupt sources to be handled by separate interrupt service routines (isrs). a more detailed discussion of the interrupt vector tables is provided in section 7.1 interrupt vector table . figure 4-2: program memory organization 0 8 16 pc address 0x000000 0x000002 0x000004 0x000006 23 00000000 00000000 00000000 00000000 program memory phantom byte (read as 0 ) least significant word most significant word instruction width 0x000001 0x000003 0x000005 0x000007 msw address (lsw address) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 37 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.2 data address space the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj1 28gpx02/x04 cpu has a separate 16-bit-wide data memory space. the data space is accessed using separate address generation units (agus) for read and write operations. the data memory maps is shown in figure 4-4 . all effective addresses (eas) in the data memory space are 16 bits wide and point to bytes within the data space. this arrangement gives a data space address range of 64 kbytes or 32k words. the lower half of the data memory space (that is, when ea<15> = 0 ) is used for implemented memory addresses, while the upper half (ea<15> = 1 ) is reserved for the program space visibility area (see section 4.8.3 reading data from program memory using program space visibility ). dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices implement up to 16 kbytes of data memory. should an ea point to a location outside of this area, an all-zero word or byte is returned. 4.2.1 data space width the data memory space is organized in byte addressable, 16-bit wide blocks. data is aligned in data memory and registers as 16-bit words, but all data space eas resolve to bytes. the least significant bytes (lsbs) of each word have even addresses, while the most significant bytes (msbs) have odd addresses. 4.2.2 data memory organization and alignment to maintain backward compatibility with pic ? mcu devices and improve data space memory usage efficiency, the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 instruction set supports both word and byte operations. as a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. for example, the core recognizes that post-modified register indirect addressing mode [ws++] resu lts in a value of ws + 1 for byte operations and ws + 2 for word operations. a data byte read, reads the complete word that contains the byte, using the lsb of any ea to determine which byte to select. the selected byte is placed onto the lsb of the data path. that is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. data byte writes only write to the corresponding side of the array or register that matches the byte address. all word accesses must be aligned to an even address. misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit mcu code. if a misaligned read or write is attempted, an address error trap is generated. if the e rror occurred on a read, the instruction underway is completed. if the error occurred on a write, the instruction is executed but the write does not occur. in either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address fault. all byte loads into any w register are loaded into the least significant byte. the most significant byte is not modified. a sign-extend instruction ( se ) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. alternatively, for 16-bit unsigned data, user applications can clear the msb of any w register by executing a zero-extend ( ze ) instruction on the appropriate address. 4.2.3 sfr space the first 2 kbytes of the near data space, from 0x0000 to 0x07ff, is primarily occupied by special function registers (sfrs). these are used by the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 core and peripheral modules for controlling the operation of the device. sfrs are distributed amon g the modules that they control, and are generally grouped together by module. much of the sfr space contains unused addresses; these are read as 0 . 4.2.4 near data space the 8 kbyte area between 0x0000 and 0x1fff is referred to as the near data space. locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. additionally, the whole data space is addressable using mov instructions, which support memory direct addressing mode with a 16-bit address field, or by using indirect addressing mode using a working register as an address pointer. note: the actual set of peripheral features and interrupts varies by the device. refer to the corresponding device tables and pinout diagrams fo r device-specific information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 38 ? 2007-2012 microchip technology inc. figure 4-3: data memory map for dspic33f j32gp302/304 devic es with 4 kb ram 0x0000 0x07fe sfr space 0xfffe x data ram (x) 16 bits lsb msb 0xffff x data optionally mapped into program memory unimplemented (x) 0x0800 2 kbyte sfr space 0x1000 0x0ffe 0x17fe 0x1800 4 kbyte sram space y data ram (y) near data 6 kbyte space 0x13fe 0x1400 lsb address msb address dma ram 0x0000 0x07ff 0x0801 0x1001 0x0fff 0x17ff 0x1801 0x13ff 0x1401 0x8001 0x8000 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 39 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 4-4: data memory map for dspic3 3fj128gp202/204 and dspic33fj64gp202/ 204 devices with 8 kb ram 0x0000 0x07fe 0x17fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0x17ff 0xffff optionally mapped into program memory 0x27ff 0x27fe 0x0801 0x0800 0x1801 0x1800 2 kbyte sfr space 8 kbyte sram space 0x8001 0x8000 0x2800 0x2801 0x1ffe 0x2000 0x1fff 0x2001 space data near 8 kbyte sfr space x data ram (x) x data unimplemented (x) dma ram y data ram (y) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 40 ? 2007-2012 microchip technology inc. figure 4-5: data memory map for dspic3 3fj128gp802/804 and dspic33fj64gp802/ 804 devices with 16 kb ram 0x0000 0x07fe 0x27fe 0xfffe lsb address 16 bits lsb msb msb address 0x0001 0x07ff 0x27ff 0xffff optionally mapped into program memory 0x47ff 0x47fe 0x0801 0x0800 0x2801 0x2800 near data 2 kbyte sfr space 16 kbyte sram space 8 kbyte space 0x8001 0x8000 0x4800 0x4801 0x3ffe 0x4000 0x3fff 0x4001 0x1ffe 0x1fff sfr space x data ram (x) x data unimplemented (x) dma ram y data ram (y) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 41 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.2.5 x and y data spaces the core has two data spaces, x and y. these data spaces can be considered either separate (for some dsp instructions), or as one unified linear address range (for mcu instructions). the data spaces are accessed using two address generation units (agus) and separate data paths. this feature allows certain instructions to concurrently fetch two words from ram, thereby enabling efficient ex ecution of dsp algorithms such as finite impulse response (fir) filtering and fast fourier transform (fft). the x data space is used by all instructions and supports all addressing modes. x data space has separate read and write data buses. the x read data bus is the read data path for all instructions that view data space as combined x and y address space. it is also the x data prefetch pa th for the dual operand dsp instructions ( mac class). the y data space is used in concert with the x data space by the mac class of instructions ( clr, ed, edac, mac, movsac, mpy, mpy.n and msc ) to provide two concurrent data read paths. both the x and y data spaces support modulo addressing mode for all instructions, subject to addressing mode restrictions . bit-reversed addressing mode is only supported for writes to x data space. all data memory writes, including in dsp instructions, view data space as combined x and y address space. the boundary between the x and y data spaces is device-dependent and is not user-programmable. all effective addresses are 16 bits wide and point to bytes within the data space. therefore, the data space address range is 64 kbytes, or 32k words, though the implemented memory locations vary by device. 4.2.6 dma ram every dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 device contains up to 2 kbytes of dual ported dma ram located at the end of y data space, and is part of y data space. memory locations in the dma ram space are accessible simultaneously by the cpu and the dma controller module. dma ram is utilized by the dma controller to store data to be transferred to various peripherals using dma, as well as data transferred from various peripherals using dma. the dma ram can be accessed by the dma controller without having to steal cycles from the cpu. when the cpu and the dma controller attempt to concurrently write to the same dma ram location, the hardware ensures that the cpu is given precedence in accessing the dma ram location. therefore, the dma ram provides a reliable means of transferring dma data without ever having to stall the cpu. 4.3 memory resources many useful resources related to memory organization are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 4.3.1 key resources section 2. program memory (ds70203) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: dma ram can be used for general purpose data storage if the dma function is not required in an application. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 42 ? 2007-2012 microchip technology inc. 4.4 special function register maps table 4-1: cpu core registers map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets wreg0 0000 working register 0 0000 wreg1 0002 working register 1 0000 wreg2 0004 working register 2 0000 wreg3 0006 working register 3 0000 wreg4 0008 working register 4 0000 wreg5 000a working register 5 0000 wreg6 000c working register 6 0000 wreg7 000e working register 7 0000 wreg8 0010 working register 8 0000 wreg9 0012 working register 9 0000 wreg10 0014 working register 10 0000 wreg11 0016 working register 11 0000 wreg12 0018 working register 12 0000 wreg13 001a working register 13 0000 wreg14 001c working register 14 0000 wreg15 001e working register 15 0800 splim 0020 stack pointer limit register xxxx accal 0022 accal xxxx accah 0024 accah xxxx accau 0026 acca<39> accau xxxx accbl 0028 accbl xxxx accbh 002a accbh xxxx accbu 002c accb<39> accbu xxxx pcl 002e program counter low word register xxxx pch 0030 program counter high byte register 0000 tblpag 0032 table page address pointer register 0000 psvpag 0034 program memory visibility page address pointer register 0000 rcount 0036 repeat loop counter register xxxx dcount 0038 dcount<15:0> xxxx dostartl 003a dostartl<15:1> 0 xxxx dostarth 003c dostarth<5:0> 00xx doendl 003e doendl<15:1> 0 xxxx doendh 0040 doendh 00xx sr 0042 oa ob sa sb oab sab da dc ipl<2:0> ra n ov z c 0000 corcon 0044 us edt dl<2:0> sata satb satdw accsat ipl3 psv rnd if 0020 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 43 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 modcon 0046 xmoden ymoden bwm<3:0> ywm<3:0> xwm<3:0> 0000 xmodsrt 0048 xs<15:1> 0 xxxx xmodend 004a xe<15:1> 1 xxxx ymodsrt 004c ys<15:1> 0 xxxx ymodend 004e ye<15:1> 1 xxxx xbrev 0050 bren xb<14:0> xxxx disicnt 0052 disable interrupts counter register xxxx table 4-1: cpu core registers map (continued) sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 44 ? 2007-2012 microchip technology inc. table 4-2: change notification regist er map for dspic33fj128gp202/802, dspic33fj64gp202/802 and dspic33fj32gp302 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 cn30ie cn29ie cn27ie cn24ie cn23ie cn22ie cn21ie cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a cn30pue cn29pue cn27pue cn24pue cn23pue cn22pue cn21pue cn16pue 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-3: change notification regist er map for dspic33fj128gp204/804, dspic33fj64gp204/804 and dspic33fj32gp304 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 all resets cnen1 0060 cn15ie cn14ie cn13ie cn12ie cn11ie cn10ie cn9ie cn8ie cn7ie cn6ie cn5ie cn4ie cn3ie cn2ie cn1ie cn0ie 0000 cnen2 0062 cn30ie cn29ie cn28ie cn27ie cn26ie cn25ie cn24ie cn23ie cn22ie cn21ie cn20ie cn19ie cn18ie cn17ie cn16ie 0000 cnpu1 0068 cn15pue cn14pue cn13pue cn12pue cn11pue cn10pue cn9pue cn8pue cn7pue cn6pue cn5pue cn4pue cn3pue cn2pue cn1pue cn0pue 0000 cnpu2 006a cn30pue cn29pue cn28pue cn27pue cn26pue cn25pue cn24pue cn23pue cn22pue cn21pue cn20pue cn19pue cn18pue cn17pue cn16pue 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 45 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-4: interrupt controller register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets intcon1 0080 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte sf tacerr div0err dmacerr matherr addrerr stkerr oscfail 0000 intcon2 0082 altivt disi int2ep int1ep int0ep 0000 ifs0 0084 dma1if ad1if u1txif u1rxif spi1if spi1eif t3if t2if oc2if ic2if dma0if t1if oc1if ic1if int0if 0000 ifs1 0086 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if ic8if ic7if int1if cnif cmif mi2c1if si2c1if 0000 ifs2 0088 dma4if pmpif dma3if c1if (1) c1rxif (1) spi2if spi2eif 0000 ifs3 008a rtcif dma5if dciif dcieif 0000 ifs4 008c dac1lif (2) dac1rif (2) c 1 t x i f (1) dma7if dma6if crcif u2eif u1eif 0000 iec0 0094 dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie t 2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie 0000 iec1 0096 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie ic8ie ic7ie int1ie cnie cmie mi2c1ie si2c1ie 0000 iec2 0098 dma4ie pmpie dma3ie c1ie (1) c1rxie (1) spi2ie spi2eie 0000 iec3 009a rtcie dma5ie dciie dcieie 0000 iec4 009c dac1lie (2) dac1rie (2) c 1 t x i e (1) dma7ie dma6ie crcie u2eie u1eie 0000 ipc0 00a4 t1ip<2:0> o c 1 i p < 2 : 0 > i c 1 i p < 2 : 0 > int0ip<2:0> 4444 ipc1 00a6 t2ip<2:0> o c 2 i p < 2 : 0 > i c 2 i p < 2 : 0 > dma0ip<2:0> 4444 ipc2 00a8 u1rxip<2:0> spi1ip<2:0> spi1eip<2:0> t3ip<2:0> 4444 ipc3 00aa dma1ip<2:0> ad1ip<2:0> u1txip<2:0> 0444 ipc4 00ac cnip<2:0> cmip<2:0> mi2c1ip<2:0> si2c1ip<2:0> 4444 ipc5 00ae i c 8 i p < 2 : 0 > i c 7 i p < 2 : 0 > int1ip<2:0> 4404 ipc6 00b0 t4ip<2:0> o c 4 i p < 2 : 0 > o c 3 i p < 2 : 0 > dma2ip<2:0> 4444 ipc7 00b2 u2txip<2:0> u2rxip<2:0> int2ip<2:0> t5ip<2:0> 4444 ipc8 00b4 c1ip<2:0> (1) c1rxip<2:0> (1) spi2ip<2:0> spi2eip<2:0> 4444 ipc9 00b6 dma3ip<2:0> 0004 ipc11 00ba dma4ip<2:0> pmpip<2:0> 0440 ipc14 00c0 dcieip<2:0> 4000 ipc15 00c2 r t c i p < 2 : 0 > dma5ip<2:0> dciip<2:0> 0444 ipc16 00c4 crcip<2:0> u2eip<2:0> u1eip<2:0> 4440 ipc17 00c6 c1txip<2:0> (1) dma7ip<2:0> dma6ip<2:0> 0444 ipc19 00ca d a c 1 l i p < 2 : 0 > (2) dac1rip<2:0> (2) 4400 inttreg 00e0 i l r < 3 : 0 > > vecnum<6:0> 4444 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: interrupts disabled on devices without ecan? modules. 2: interrupts disabled on devices without audio dac modules. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 46 ? 2007-2012 microchip technology inc. table 4-5: timer register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets tmr1 0100 timer1 register 0000 pr1 0102 period register 1 ffff t1con 0104 ton tsidl tgate tckps<1:0> tsync tcs 0000 tmr2 0106 timer2 register 0000 tmr3hld 0108 timer3 holding register (for 32-bit timer operations only) xxxx tmr3 010a timer3 register 0000 pr2 010c period register 2 ffff pr3 010e period register 3 ffff t2con 0110 ton tsidl tgate tckps<1:0> t32 tcs 0000 t3con 0112 ton tsidl tgate tckps<1:0> tcs 0000 tmr4 0114 timer4 register 0000 tmr5hld 0116 timer5 holding register (for 32-bit timer operations only) xxxx tmr5 0118 timer5 register 0000 pr4 011a period register 4 ffff pr5 011c period register 5 ffff t4con 011e ton tsidl tgate tckps<1:0> t32 tcs 0000 t5con 0120 ton tsidl tgate tckps<1:0> tcs 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-6: input capture register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets ic1buf 0140 input 1 capture register xxxx ic1con 0142 icsidl ictmr ici<1:0> icov icbne icm<2:0> 0000 ic2buf 0144 input 2 capture register xxxx ic2con 0146 icsidl ictmr ici<1:0> icov icbne icm<2:0> 0000 ic7buf 0158 input 7 capture register xxxx ic7con 015a icsidl ictmr ici<1:0> icov icbne icm<2:0> 0000 ic8buf 015c input 8capture register xxxx ic8con 015e icsidl ictmr ici<1:0> icov icbne icm<2:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 47 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-7: output compare register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets oc1rs 0180 output compare 1 secondary register xxxx oc1r 0182 output compare 1 register xxxx oc1con 0184 ocsidl ocflt octsel ocm<2:0> 0000 oc2rs 0186 output compare 2 secondary register xxxx oc2r 0188 output compare 2 register xxxx oc2con 018a ocsidl ocflt octsel ocm<2:0> 0000 oc3rs 018c output compare 3 secondary register xxxx oc3r 018e output compare 3 register xxxx oc3con 0190 ocsidl ocflt octsel ocm<2:0> 0000 oc4rs 0192 output compare 4 secondary register xxxx oc4r 0194 output compare 4 register xxxx oc4con 0196 ocsidl ocflt octsel ocm<2:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-8: i2c1 register map sfr name sfr addr b i t 1 5b i t 1 4b i t 1 3b i t 1 2b i t 1 1b i t 1 0b i t 9b i t 8b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 all resets i2c1rcv 0200 receive register 0000 i2c1trn 0202 transmit register 00ff i2c1brg 0204 baud rate generator register 0000 i2c1con 0206 i2cen i2csidl sclrel ipmien a10m disslw smen gcen stren ackdt acken rcen pen rsen sen 1000 i2c1stat 0208 ackstat trstat bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 i2c1add 020a address register 0000 i2c1msk 020c address mask register 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-9: uart1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u1mode 0220 uarten usidl iren rtsmd uen1 uen0 wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u1sta 0222 utxisel1 utxinv utxisel0 utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u1txreg 0224 utx8 uart transmit register xxxx u1rxreg 0226 urx8 uart received register 0000 u1brg 0228 baud rate generator prescaler 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 48 ? 2007-2012 microchip technology inc. table 4-10: uart2 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets u2mode 0230 uarten usidl iren rtsmd uen1 uen0 wake lpback abaud urxinv brgh pdsel<1:0> stsel 0000 u2sta 0232 utxisel1 utxinv utxisel0 utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda 0110 u2txreg 0234 utx8 uart transmit register xxxx u2rxreg 0236 urx8 uart receive register 0000 u2brg 0238 baud rate generator prescaler 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-11: spi1 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets spi1stat 0240 spien spisidl s p i r o v spitbf spirbf 0000 spi1con1 0242 dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi1con2 0244 frmen spifsd frmpol frmdly 0000 spi1buf 0248 spi1 transmit and receive buffer register 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-12: spi2 register map sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets spi2stat 0260 spien spisidl s p i r o v spitbf spirbf 0000 spi2con1 0262 dissck dissdo mode16 smp cke ssen ckp msten spre<2:0> ppre<1:0> 0000 spi2con2 0264 frmen spifsd frmpol frmdly 0000 spi2buf 0268 spi2 transmit and receive buffer register 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 49 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-13: adc1 register map fo r dspic33fj64gp202/802, dspic33f j128gp202/802 and dspic33fj32gp302 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx ad1con1 0320 adon adsidl addmabm ad12b form<1:0> ssrc<2:0> simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> cscna chps<1:0> bufs smpi<3:0> bufm alts 0000 ad1con3 0324 adrc samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ch123nb<1:0> ch123sb ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ch0sb<4:0> ch0na ch0sa<4:0> 0000 ad1pcfgl 032c pcfg12 pcfg11 pcfg10 pcfg9 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 css12 css11 css10 css9 css5 css4 css3 css2 css1 css0 0000 ad1con4 0332 dmabl<2:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-14: adc1 register map fo r dspic33fj64gp204/804, dspic33f j128gp204/804 and dspic33fj32gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 all resets adc1buf0 0300 adc data buffer 0 xxxx ad1con1 0320 adon adsidladdmabm ad12b form<1:0> ssrc<2:0> simsam asam samp done 0000 ad1con2 0322 vcfg<2:0> cscna chps<1:0> bufs smpi<3:0> bufm alts 0000 ad1con3 0324 adrc samc<4:0> adcs<7:0> 0000 ad1chs123 0326 ch123nb<1:0> ch123sb ch123na<1:0> ch123sa 0000 ad1chs0 0328 ch0nb ch0sb<4:0> ch0na ch0sa<4:0> 0000 ad1pcfgl 032c pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 0000 ad1cssl 0330 css12 css11 css10 css9 css8 css7 css6 css5 css4 css3 css2 css1 css0 0000 ad1con4 0332 dmabl<2:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-15: dac1 register map for dspic3 3fj128gp802/804 and ds pic33fj64gp802/804 sfr name sfr addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 all resets dac1con 03f0 dacen dacsidl ampon f o r m dacfdiv<6:0> 0000 dac1stat 03f2 loen l m v o e n litype lfull lempty roen r m v o e n r i t y p er f u l lr e m p t y 0000 dac1dflt 03f4 dac1dflt<15:0> 0000 dac1rdat 03f6 dac1rdat<15:0> 0000 dac1ldat 03f8 dac1ldat<15:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 50 ? 2007-2012 microchip technology inc. table 4-16: dma register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets dma0con 0380 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma0req 0382 force irqsel<6:0> 0000 dma0sta 0384 sta<15:0> 0000 dma0stb 0386 stb<15:0> 0000 dma0pad 0388 pad<15:0> 0000 dma0cnt 038a cnt<9:0> 0000 dma1con 038c chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma1req 038e force irqsel<6:0> 0000 dma1sta 0390 sta<15:0> 0000 dma1stb 0392 stb<15:0> 0000 dma1pad 0394 pad<15:0> 0000 dma1cnt 0396 cnt<9:0> 0000 dma2con 0398 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma2req 039a force irqsel<6:0> 0000 dma2sta 039c sta<15:0> 0000 dma2stb 039e stb<15:0> 0000 dma2pad 03a0 pad<15:0> 0000 dma2cnt 03a2 cnt<9:0> 0000 dma3con 03a4 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma3req 03a6 force irqsel<6:0> 0000 dma3sta 03a8 sta<15:0> 0000 dma3stb 03aa stb<15:0> 0000 dma3pad 03ac pad<15:0> 0000 dma3cnt 03ae cnt<9:0> 0000 dma4con 03b0 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma4req 03b2 force irqsel<6:0> 0000 dma4sta 03b4 sta<15:0> 0000 dma4stb 03b6 stb<15:0> 0000 dma4pad 03b8 pad<15:0> 0000 dma4cnt 03ba cnt<9:0> 0000 dma5con 03bc chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma5req 03be force irqsel<6:0> 0000 dma5sta 03c0 sta<15:0> 0000 dma5stb 03c2 stb<15:0> 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 51 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 dma5pad 03c4 pad<15:0> 0000 dma5cnt 03c6 cnt<9:0> 0000 dma6con 03c8 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma6req 03ca force irqsel<6:0> 0000 dma6sta 03cc sta<15:0> 0000 dma6stb 03ce stb<15:0> 0000 dma6pad 03d0 pad<15:0> 0000 dma6cnt 03d2 cnt<9:0> 0000 dma7con 03d4 chen size dir half nullw a m o d e < 1 : 0 > mode<1:0> 0000 dma7req 03d6 force irqsel<6:0> 0000 dma7sta 03d8 sta<15:0> 0000 dma7stb 03da stb<15:0> 0000 dma7pad 03dc pad<15:0> 0000 dma7cnt 03de cnt<9:0> 0000 dmacs0 03e0 pwcol7 pwcol6 pwcol5 pwcol4 pwcol3 pwcol2 pwcol1 pwcol0 xwcol7 xwcol6 xwcol5 xwcol4 xwcol3 xwcol2 xwcol1 xwcol0 0000 dmacs1 03e2 lstch<3:0> ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 0000 dsadr 03e4 dsadr<15:0> 0000 table 4-16: dma register map (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 52 ? 2007-2012 microchip technology inc. table 4-17: ecan1 register map when c1ctrl1.win = 0 or 1 (for dspic33fj128gp802/804 and dspic33fj64gp802/804) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 b it 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets c1ctrl1 0400 csidl abat reqop<2:0> opmode<2:0> cancap w i n 0480 c1ctrl2 0402 dncnt<4:0> 0000 c1vec 0404 filhit<4:0> i c o d e < 6 : 0 > 0000 c1fctrl 0406 dmabs<2:0> fsa<4:0> 0000 c1fifo 0408 fbp<5:0> fnrb<5:0> 0000 c1intf 040a txbo txbp rxbp txwar rxwar ewarn ivrif wakif errif fifoif rbovif rbif tbif 0000 c1inte 040c ivrie wakie errie fifoie rbovie rbie tbie 0000 c1ec 040e terrcnt<7:0> rerrcnt<7:0> 0000 c1cfg1 0410 sjw<1:0> brp<5:0> 0000 c1cfg2 0412 w a k f i l seg2ph<2:0> seg2phts sam seg1ph<2:0> prseg<2:0> 0000 c1fen1 0414 flten15 flten14 flten13 flten12 flten11 flten10 flten9 flten8 flten7 flten6 flten5 flten4 flte n3 flten2 flten1 flten0 ffff c1fmsksel1 0418 f7msk<1:0> f6msk<1:0> f5msk<1:0> f4msk<1:0> f3msk<1:0> f2msk<1:0> f1msk<1:0> f0msk<1:0> 0000 c1fmsksel2 041a f15msk<1:0> f14msk<1:0> f13msk<1:0> f12msk<1:0> f11msk<1:0> f10msk<1:0> f9msk<1:0> f8msk<1:0> 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-18: ecan1 register map when c1ctrl1.win = 0 (for dspic33fj128gp802/804 and dspic33fj64gp802/804) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 all resets 0400- 041e see definition when win = x c1rxful1 0420 rxful15 rxful14 rxful13 rxful12 rxful11 rxful10 rxfu l9 rxful8 rxful7 rxful6 rxful5 rxful4 rxful3 rxful2 rxful1 rxful0 0000 c1rxful2 0422 rxful31 rxful30 rxful29 rxful28 rxful27 rxful26 rxful25 rxful24 r xful23 rxful22 rxful21 rxful20 rxful19 rxful18 rxful17 rxful16 0000 c1rxovf1 0428 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxov f9 rxovf8 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 0000 c1rxovf2 042a rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf 25 rxovf24 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 0000 c1tr01con 0430 txen1 txabt1 txlarb1 txerr1 txreq1 rtren1 tx1pri<1:0> txen0 txabt0 txlarb0 txerr0 txreq0 rtren0 tx0pri<1:0> 0000 c1tr23con 0432 txen3 txabt3 txlarb3 txerr3 txreq3 rtren3 tx3pri<1:0> txen2 txabt2 txlarb2 txerr2 txreq2 rtren2 tx2pri<1:0> 0000 c1tr45con 0434 txen5 txabt5 txlarb5 txerr5 txreq5 rtren5 tx5pri<1:0> txen4 txabt4 txlarb4 txerr4 txreq4 rtren4 tx4pri<1:0> 0000 c1tr67con 0436 txen7 txabt7 txlarb7 txerr7 txreq7 rtren7 tx7pri<1:0> txen6 txabt6 txlarb6 txerr6 txreq6 rtren6 tx6pri<1:0> 0000 c1rxd 0440 received data word xxxx c1txd 0442 transmit data word xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 53 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-19: ecan1 register map when c1ctrl1.win = 1 (for dspic33fj128gp802/804 and dspic33fj64gp802/804) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets 0400- 041e see definition when win = x c1bufpnt1 0420 f3bp<3:0> f2bp<3:0> f1bp<3:0> f0bp<3:0> 0000 c1bufpnt2 0422 f7bp<3:0> f6bp<3:0> f5bp<3:0> f4bp<3:0> 0000 c1bufpnt3 0424 f11bp<3:0> f10bp<3:0> f9bp<3:0> f8bp<3:0> 0000 c1bufpnt4 0426 f15bp<3:0> f14bp<3:0> f13bp<3:0> f12bp<3:0> 0000 c1rxm0sid 0430 sid<10:3> sid<2:0> m i d e eid<17:16> xxxx c1rxm0eid 0432 eid<15:8> eid<7:0> xxxx c1rxm1sid 0434 sid<10:3> sid<2:0> m i d e eid<17:16> xxxx c1rxm1eid 0436 eid<15:8> eid<7:0> xxxx c1rxm2sid 0438 sid<10:3> sid<2:0> m i d e eid<17:16> xxxx c1rxm2eid 043a eid<15:8> eid<7:0> xxxx c1rxf0sid 0440 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf0eid 0442 eid<15:8> eid<7:0> xxxx c1rxf1sid 0444 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf1eid 0446 eid<15:8> eid<7:0> xxxx c1rxf2sid 0448 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf2eid 044a eid<15:8> eid<7:0> xxxx c1rxf3sid 044c sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf3eid 044e eid<15:8> eid<7:0> xxxx c1rxf4sid 0450 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf4eid 0452 eid<15:8> eid<7:0> xxxx c1rxf5sid 0454 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf5eid 0456 eid<15:8> eid<7:0> xxxx c1rxf6sid 0458 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf6eid 045a eid<15:8> eid<7:0> xxxx c1rxf7sid 045c sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf7eid 045e eid<15:8> eid<7:0> xxxx c1rxf8sid 0460 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf8eid 0462 eid<15:8> eid<7:0> xxxx c1rxf9sid 0464 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf9eid 0466 eid<15:8> eid<7:0> xxxx c1rxf10sid 0468 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf10eid 046a eid<15:8> eid<7:0> xxxx c1rxf11sid 046c sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 54 ? 2007-2012 microchip technology inc. c1rxf11eid 046e eid<15:8> eid<7:0> xxxx c1rxf12sid 0470 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf12eid 0472 eid<15:8> eid<7:0> xxxx c1rxf13sid 0474 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf13eid 0476 eid<15:8> eid<7:0> xxxx c1rxf14sid 0478 sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf14eid 047a eid<15:8> eid<7:0> xxxx c1rxf15sid 047c sid<10:3> sid<2:0> e x i d e eid<17:16> xxxx c1rxf15eid 047e eid<15:8> eid<7:0> xxxx table 4-19: ecan1 register map when c1ctrl1.win = 1 (for dspic33fj128gp802/804 and ds pic33fj64gp802/804) (continued) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-20: dci register map sfr name addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state dcicon1 0280 dcien dcisidl dloop csckd cscke cofsd unfm csdom djst cofsm1cofsm0 0000 0000 0000 0000 dcicon2 0282 b l e n 1b l e n 0 c o f s g < 3 : 0 > ws<3:0> 0000 0000 0000 0000 dcicon3 0284 b c g < 1 1 : 0 > 0000 0000 0000 0000 dcistat 0286 s l o t 3s l o t 2s l o t 1s l o t 0 rov rful tunf tmpty 0000 0000 0000 0000 tscon 0288 tse15 tse14 tse13 tse12 tse11 tse10 tse9 tse8 tse7 tse6 tse5 tse4 tse3 tse2 tse1 tse0 0000 0000 0000 0000 rscon 028c rse15 rse14 rse13 rse12 rse11 rse10 rse9 rse8 rse7 rse6 rse5 rse4 rse3 rse2 rse1 rse0 0000 0000 0000 0000 rxbuf0 0290 receive buffer 0 data register 0000 0000 0000 0000 rxbuf1 0292 receive buffer 1 data register 0000 0000 0000 0000 rxbuf2 0294 receive buffer 2 data register 0000 0000 0000 0000 rxbuf3 0296 receive buffer 3 data register 0000 0000 0000 0000 txbuf0 0298 transmit buffer 0 data register 0000 0000 0000 0000 txbuf1 029a transmit buffer 1 data register 0000 0000 0000 0000 txbuf2 029c transmit buffer 2 data register 0000 0000 0000 0000 txbuf3 029e transmit buffer 3 data register 0000 0000 0000 0000 legend: = unimplemented, read as 0 . downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 55 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-21: peripheral pin select input register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpinr0 0680 int1r<4:0> 1f00 rpinr1 0682 i n t 2 r < 4 : 0 > 001f rpinr3 0686 t 3 c k r < 4 : 0 > t 2 c k r < 4 : 0 > 1f1f rpinr4 0688 t 5 c k r < 4 : 0 > t 4 c k r < 4 : 0 > 1f1f rpinr7 068e ic2r<4:0> ic1r<4:0> 1f1f rpinr10 0694 ic8r<4:0> ic7r<4:0> 1f1f rpinr11 0696 o c f a r < 4 : 0 > 001f rpinr18 06a4 u1ctsr<4:0> u 1 r x r < 4 : 0 > 1f1f rpinr19 06a6 u2ctsr<4:0> u 2 r x r < 4 : 0 > 1f1f rpinr20 06a8 s c k 1 r < 4 : 0 > s d i 1 r < 4 : 0 > 1f1f rpinr21 06aa ss1r<4:0> 001f rpinr22 06ac s c k 2 r < 4 : 0 > s d i 2 r < 4 : 0 > 1f1f rpinr23 06ae ss2r<4:0> 001f rpinr24 06b0 csckr<4:0> c s d i r < 4 : 0 > 1f1f rpinr25 06b2 c o f s r < 4 : 0 > 001f rpinr26 (1) 06b4 c 1 r x r < 4 : 0 > 001f legend: x = unknown value on reset, = unimplemented, read as 0. reset values are shown in hexadecimal. note 1: this register is present only for dspi c33fj128gp802/804 and dspic33fj64gp802/804 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 56 ? 2007-2012 microchip technology inc. table 4-22: peripheral pin select output register map for dspic33fj128gp202/802, dspic33fj64gp202/802 and dspic33fj32gp302 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 rp1r<4:0> rp0r<4:0> 0000 rpor1 06c2 rp3r<4:0> rp2r<4:0> 0000 rpor2 06c4 rp5r<4:0> rp4r<4:0> 0000 rpor3 06c6 rp7r<4:0> rp6r<4:0> 0000 rpor4 06c8 rp9r<4:0> rp8r<4:0> 0000 rpor5 06ca r p 1 1 r < 4 : 0 > rp10r<4:0> 0000 rpor6 06cc r p 1 3 r < 4 : 0 > rp12r<4:0> 0000 rpor7 06ce r p 1 5 r < 4 : 0 > rp14r<4:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-23: peripheral pin select output register map for dspic33fj128gp204/804, dspic33fj64gp204/804 and dspic33fj32gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rpor0 06c0 rp1r<4:0> rp0r<4:0> 0000 rpor1 06c2 rp3r<4:0> rp2r<4:0> 0000 rpor2 06c4 rp5r<4:0> rp4r<4:0> 0000 rpor3 06c6 rp7r<4:0> rp6r<4:0> 0000 rpor4 06c8 rp9r<4:0> rp8r<4:0> 0000 rpor5 06ca r p 1 1 r < 4 : 0 > rp10r<4:0> 0000 rpor6 06cc r p 1 3 r < 4 : 0 > rp12r<4:0> 0000 rpor7 06ce r p 1 5 r < 4 : 0 > rp14r<4:0> 0000 rpor8 06d0 r p 1 7 r < 4 : 0 > rp16r<4:0> 0000 rpor9 06d2 r p 1 9 r < 4 : 0 > rp18r<4:0> 0000 rpor10 06d4 r p 2 1 r < 4 : 0 > rp20r<4:0> 0000 rpor11 06d6 r p 2 3 r < 4 : 0 > rp22r<4:0> 0000 rpor12 06d8 r p 2 5 r < 4 : 0 > rp24r<4:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 57 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-24: parallel master/slave po rt register map for dspic33fj128g p202/802, dspic33fj64gp202/802 and dspic33fj32gp302 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmcon 0600 pmpen psidl adrmux<1:0> ptbeen ptwren ptrden csf1 csf0 alp cs1p bep wrsp rdsp 0000 pmmode 0602 busy irqm<1:0> incm<1:0> mode16 mo de<1:0> waitb<1:0> wai tm<3:0> waite<1:0> 0000 pmaddr 0604 addr15 cs1 addr<13:0> 0000 pmdout1 parallel port data out register 1 (buffers 0 and 1) 0000 pmdout2 0606 parallel port data out register 2 (buffers 2 and 3) 0000 pmdin1 0608 parallel port data in register 1 (buffers 0 and 1) 0000 pmpdin2 060a parallel port data in register 2 (buffers 2 and 3) 0000 pmaen 060c p t e n 1 4 pten<1:0> 0000 pmstat 060e ibf ibov ib3f ib2f ib1f ib0f obe obuf ob3e ob2e ob1e ob0e 008f legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-25: parallel master/slave po rt register map for dspic33fj128g p204/804, dspic33fj64gp204/804 and dspic33fj32gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets pmcon 0600 pmpen psidl adrmux<1:0> ptbeen ptwren ptrden csf1 csf0 alp cs1p bep wrsp rdsp 0000 pmmode 0602 busy irqm<1:0> incm<1:0> mode16 mo de<1:0> waitb<1:0> wai tm<3:0> waite<1:0> 0000 pmaddr 0604 addr15 cs1 addr<13:0> 0000 pmdout1 parallel port data out register 1 (buffers 0 and 1) 0000 pmdout2 0606 parallel port data out register 2 (buffers 2 and 3) 0000 pmdin1 0608 parallel port data in register 1 (buffers 0 and 1) 0000 pmpdin2 060a parallel port data in register 2 (buffers 2 and 3) 0000 pmaen 060c p t e n 1 4 pten<10:0> 0000 pmstat 060e ibf ibov ib3f ib2f ib1f ib0f obe obuf ob3e ob2e ob1e ob0e 008f legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 58 ? 2007-2012 microchip technology inc. table 4-26: real-time clock and calendar register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 all resets alrmval 0620 alarm value register window based on aptr<1:0> xxxx alcfgrpt 0622 alrmen chime amask<3:0> alrmptr<1:0> arpt<7:-0> 0000 rtcval 0624 rtcc value register window based on rtcptr<1:0> xxxx rcfgcal 0626 rtcen rtcwren rtcsync halfsec rtcoe rtcptr<1:0> cal<7:0> 0000 padcfg1 02fc rtsecsel pmpttl 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-27: crc register map f i l e n a m ea d d rb i t 1 5b i t 1 4b i t 1 3b i t 1 2b i t 1 1b i t 1 0b i t 9b i t 8b i t 7b i t 6b i t 5b i t 4b i t 3b i t 2b i t 1b i t 0 all resets crccon 0640 csidl vword<4:0> crcful crcmpt crcgo plen<3:0> 0000 crcxor 0642 x<15:0> 0000 crcdat 0644 crc data input register 0000 crcwdat 0646 crc result register 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-28: dual comparator register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets cmcon 0630 cmidl c2evt c1evt c2en c1en c2outen c1outen c2out c1out c2inv c1inv c2neg c2pos c1neg c1pos 0000 cvrcon 0632 cvren cvroe cvrr cvrss cvr<3:0> 0000 legend: = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-29: porta register map fo r dspic33fj128gp202/802, dspic33f j64gp202/802 and dspic33fj32gp302 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 all resets trisa 02c0 trisa4 trisa3 trisa2 trisa1 trisa0 001f porta 02c2 ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 59 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 4-30: porta register map fo r dspic33fj128gp204/804, dspic33f j64gp204/804 and dspic33fj32gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisa 02c0 trisa10 trisa9 trisa8 trisa7 trisa4 trisa3 trisa2 trisa1 trisa0 079f porta 02c2 ra10 ra9 ra8 ra7 ra4 ra3 ra2 ra1 ra0 xxxx lata 02c4 lata10 lata9 lata8 lata7 lata4 lata3 lata2 lata1 lata0 xxxx odca 02c6 odca10 odca9 odca8 odca7 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-31: portb register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisb 02c8 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 tris b5 trisb4 trisb3 trisb2 trisb1 trisb0 ffff portb 02ca rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb 0 xxxx latb 02cc latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 l atb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx odcb 02ce odcb11 odcb10 odcb9 odcb8 odcb7 odcb6 odcb5 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-32: portc register map for dspic33fj128gp204/8 04, dspic33fj64gp204/80 4 and dspic33fj32gp304 file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets trisc 02d0 trisc9 trisc8 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 03ff portc 02d2 rc9 rc8 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx latc 02d4 latc9 latc8 latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx odcc 02d6 odcc9 odcc8 odcc7 odcc6 odcc5 odcc4 odcc3 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 60 ? 2007-2012 microchip technology inc. table 4-33: system control register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets rcon 0740 trapr iopuwr cm vregs extr swr swdten wdto sleep idle bor por xxxx (1) osccon 0742 cosc<2:0> nosc<2:0> clklock iolock lock c f lposcen oswen 0300 (2) clkdiv 0744 roi doze<2:0> dozen frcdiv<2:0> pllpost<1:0> pllpre<4:0> 3040 pllfbd 0746 plldiv<8:0> 0030 osctun 0748 tun<5:0> 0000 aclkcon 074a selaclk aoscmd<1:0> apstsclr<2:0> asrcsel 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: rcon register reset values dependent on type of reset. 2: osccon register reset values dependent on the fo sc configuration bits and by type of reset. table 4-34: security register map (1) file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets bsram 0750 iw_bsr ir_bsr rl_bsr 0000 ssram 0752 iw_ ssr ir_ssr rl_ssr 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. note 1: this register is not present in devices with 4k ram and 32k flash memory. table 4-35: nvm register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 all resets nvmcon 0760 wr wren wrerr e r a s e n v m o p < 3 : 0 > 0000 nvmkey 0766 nvmkey<7:0> 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. table 4-36: pmd register map file name addr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bi t 3 bit 2 bit 1 bit 0 all resets pmd1 0770 t5md t4md t3md t2md t1md dcimd i2c1md u2md u1md spi2md spi1md c1md ad1md 0000 pmd2 0772 ic8md ic7md i c 2 m di c 1 m d oc4md oc3md oc2md oc1md 0000 pmd3 0774 cmpmd rtccmd pmpmd crcmd dac1md 0000 legend: x = unknown value on reset, = unimplemented, read as 0 . reset values are shown in hexadecimal. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 61 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.4.1 software stack in addition to its use as a working register, the w15 register in the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices is also used as a software stack pointer. the stack pointer always points to the first available free word and grows from lower to higher addresses. it pre-decrements for stack pops and post-increments for stack pushes, as shown in figure 4-6 . for a pc push during any call instruction, the msb of the pc is zero- extended before the push, ensuring that the msb is always clear. the stack pointer limit r egister (splim) associated with the stack pointer sets an upper address boundary for the stack. splim is uninitialized at reset. as is the case for the stack pointer, splim<0> is forced to 0 because all stack operations must be word aligned. whenever an ea is generated using w15 as a source or destination pointer, the resulting address is compared with the value in splim. if the contents of the stack pointer (w15) and the splim register are equal and a push operation is performed, a stack error trap does not occur. the stack error trap occurs on a subsequent push operation. fo r example, to cause a stack error trap when the stack grows beyond address 0x2000 in ram, initialize the splim with the value 0x1ffe. similarly, a stack pointer underflow (stack error) trap is generated when the stack pointer address is found to be less than 0x0800. this prevents the stack from interfering with the special function register (sfr) space. a write to the splim register should not be immediately followed by an indirect read operation using w15. figure 4-6: call stack frame 4.4.2 data ram protection feature the dspic33f product family supports data ram protection features that en able segments of ram to be protected when used in conjunction with boot and secure code segment security. bsram (secure ram segment for bs) is accessible only from the boot segment flash code when enabled. ssram (secure ram segment for ram) is accessible only from the secure segment flash code when enabled. see table 4-1 for an overview of the bsram and ssram sfrs. 4.5 instruction addressing modes the addressing modes shown in table 4-37 form the basis of the addressing modes optimized to support the specific features of i ndividual instructions. the addressing modes provided in the mac class of instructions differ from th ose in the other instruction types. 4.5.1 file register instructions most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). most file register instructions employ a working register, w0, which is denoted as wreg in these instructions. the destination is typically either the same file register or wreg (with the exception of the mul instruction), which writes the result to a register or register pair. the mov instruction allows additional flexibility and can access the entire data space. 4.5.2 mcu instructions the three-operand mcu instru ctions are of the form: operand 3 = operand 1 dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 62 ? 2007-2012 microchip technology inc. table 4-37: fundamental addressing modes supported 4.5.3 move and accumulator instructions move instructions and the dsp accumulator class of instructions provide a great er degree of addressing flexibility than other instructions. in addition to the addressing modes supported by most mcu instructions, move and accu mulator instructions also support register indire ct with register offset addressing mode, also referred to as register indexed mode. in summary, the following addressing modes are supported by move and accumulator instructions: register direct register indirect register indirect post-modified register indirect pre-modified register indirect with register offset (indexed) register indirect with literal offset 8-bit literal 16-bit literal 4.5.4 mac instructions the dual source operand dsp instructions ( clr , ed , edac , mac , mpy , mpy.n , movsac and msc ), also referred to as mac instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. the two-source operand pref etch registers must be members of the set {w8, w9, w10, w11}. for data reads, w8 and w9 are always directed to the x ragu, and w10 and w11 are always directed to the y agu. the effective addresses generated (before and after modification) must, therefore, be valid addresses within x data space for w8 and w9 and y data space for w10 and w11. in summary, the following addressing modes are supported by the mac class of instructions: register indirect register indirect post-modified by 2 register indirect post-modified by 4 register indirect post-modified by 6 register indirect with register offset (indexed) 4.5.5 other instructions besides the addressing modes outlined previously, some instructions use literal cons tants of various sizes. for example, bra (branch) instructions use 16-bit signed lit- erals to specify the branch destination directly, whereas the disi instruction uses a 14-bit unsigned literal field. in some instructions, such as add acc , the source of an operand or result is implied by the opcode itself. certain operations, such as nop , do not have any operands. addressing mode description file register direct the address of the file register is specified explicitly. register direct the contents of a register are accessed directly. register indirect the contents of wn forms the effective address (ea). register indirect post-modified the contents of wn forms the ea. wn is post-modified (incremented or decremented) by a constant value. register indirect pre-modified wn is pre-modified (incremented or decremented) by a signed constant value to form the ea. register indirect with register offset (register indexed) the sum of wn and wb forms the ea. register indirect with literal offset the sum of wn and a literal forms the ea. note: for the mov instructions, the addressing mode specified in the instruction can differ for the source and destination ea. however, the 4-bit wb (register offset) field is shared by both source and destination (but typically only used by one). note: not all instructions support all the address- ing modes given above. individual instruc- tions may support different subsets of these addressing modes. note: register indirect with register offset addressing mode is available only for w9 (in x space) and w11 (in y space). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 63 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.6 modulo addressing modulo addressing mode is a method of providing an automated means to support circular data buffers using hardware. the objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many dsp algorithms. modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). one circular buffer can be supported in each of the x (which also provides the pointers into program space) and y data spaces. modulo addressing can operate on any w register pointer. however, it is not advisable to use w14 or w15 for modulo addressing since these two registers ar e used as the stack frame pointer and stack pointer, respectively. in general, any particular circular buffer can be config- ured to operate in only one direction as there are certain restrictions on the bu ffer start address (for incre- menting buffers), or end address (for decrementing buffers), based upon the direction of the buffer. the only exception to the usage restrictions is for buffers that have a power-of-two length. as these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performe d on both the lower and upper address boundaries). 4.6.1 start and end address the modulo addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit modulo buffer address registers: xmodsrt, xmodend, ymodsrt and ymodend (see ta b l e 4 - 1 ). the length of a circular buffer is not directly specified. it is determined by the difference between the corresponding start and end addresses. the maximum possible length of the circular buffer is 32k words (64 kbytes). 4.6.2 w address register selection the modulo and bit-reversed addressing control register, modcon<15:0>, contains enable flags as well as a w register field to sp ecify the w address registers. the xwm and ywm fields select the registers that operate with modulo addressing: if xwm = 15 , x ragu and x wagu modulo addressing is disabled. if ywm = 15 , y agu modulo addressing is disabled. the x address space pointer w register (xwm), to which modulo addressing is to be applied, is stored in modcon<3:0> (see table 4-1 ). modulo addressing is enabled for x data space when xwm is set to any value other than 15 and the xmoden bit is set at modcon<15>. the y address space pointer w register (ywm) to which modulo addressing is to be applied is stored in modcon<7:4>. modulo addressing is enabled for y data space when ywm is set to any value other than 15 and the ymoden bit is set at modcon<14>. figure 4-7: modulo addr essing operation example note: y space modulo addressing ea calculations assume word-sized data (lsb of every ea is always clear). 0x1100 0x1163 start addr = 0x1100 end addr = 0x1163 length = 0x0032 words byte address mov #0x1100, w0 mov w0, xmodsrt ;set modulo start address mov #0x1163, w0 mov w0, modend ;set modulo end address mov #0x8001, w0 mov w0, modcon ;enable w1, x agu for modulo mov #0x0000, w0 ;w0 holds buffer fill value mov #0x1110, w1 ;point w1 to buffer do again, #0x31 ;fill the 50 buffer locations mov w0, [w1++] ;fill the next location again: inc w0, w0 ;increment the fill value downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 64 ? 2007-2012 microchip technology inc. 4.6.3 modulo addressing applicability modulo addressing can be applied to the effective address (ea) calculation associated with any w register. address boundaries check for addresses equal to: the upper boundary addresses for incrementing buffers the lower boundary addresses for decrementing buffers it is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). address changes can, therefore, jump beyond boundaries and still be adjusted correctly. 4.7 bit-reversed addressing bit-reversed addressing mode is intended to simplify data reordering for radix-2 fft algorithms. it is supported by the x agu for data writes only. the modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. the address source and destination are kept in normal order. thus, the only operand requiring reversal is the modifier. 4.7.1 bit-reverse d addressing implementation bit-reversed addressing mode is enabled in any of these situations: bwm bits (w register selection) in the modcon register are any value other than 15 (the stack cannot be accessed using bit-reversed addressing) the bren bit is set in the xbrev register the addressing mode used is register indirect with pre-increment or post-increment if the length of a bit-reversed buffer is m = 2 n bytes, the last n bits of the data buffer start address must be zeros. xb<14:0> is the bit-reversed address modifier, or pivot point, which is typica lly a constant. in the case of an fft computation, its value is equal to half of the fft data buffer size. when enabled, bit-reversed addressing is executed only for register indirect with pre-increment or post- increment addressing and word-sized data writes. it does not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. when bit-reversed ad dressing is active, the w address pointer is always added to the address modifier (xb), and the offset associated with the register indirect addressing mode is ignored. in addition, as word-sized data is a requirement, the lsb of the ea is ignored (and always clear). if bit-reversed addressing has already been enabled by setting the bren bit (xbrev<15>), a write to the xbrev register should not be immediately followed by an indirect read operation using the w register that has been designated as the bit-reversed pointer. note: the modulo corrected effective address is written back to the register only when pre- modify or post-modify addressing mode is used to compute the effective address. when an address offset (such as [w7 + w2]) is used, modulo address correction is performed but the contents of the register remain unchanged. note: all bit-reversed ea calculations assume word-sized data (lsb of every ea is always clear). the xb value is scaled accordingly to generate compatible (byte) addresses. note: modulo addressing and bit-reversed addressing should not be enabled together. if an application attempts to do so, bit-reversed addressing assumes priority when active for the x wagu and x wagu, modulo addressing is disabled. however, modulo addressing cont inues to function in the x ragu. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 65 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 4-8: bit-reversed address example table 4-38: bit-reversed address sequence (16-entry) normal address bit-reversed address a3 a2 a1 a0 decimal a3 a2 a1 a0 decimal 0000 0 0000 0 0001 1 1000 8 0010 2 0100 4 0011 3 1100 12 0100 4 0010 2 0101 5 1010 10 0110 6 0110 6 0111 7 1110 14 1000 8 0001 1 1001 9 1001 9 1010 10 0101 5 1011 11 1101 13 1100 12 0011 3 1101 13 1011 11 1110 14 0111 7 1111 15 1111 15 b3 b2 b1 0 b2 b3 b4 0 bit locations swapped left-to-right around center of binary value bit-reversed address xb = 0x0008 for a 16-word bit-reversed buffer b7 b6 b5 b1 b7 b6 b5 b4 b11 b10 b9 b8 b11 b10 b9 b8 b15 b14 b13 b12 b15 b14 b13 b12 sequential address pivot point downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 66 ? 2007-2012 microchip technology inc. 4.8 interfacing program and data memory spaces the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 architecture uses a 24 bit wide program space and a 16 bit wide data space. the architecture is also a modified harvard scheme, meaning that data ca n also be present in the program space. to use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. aside from normal execution, the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 architecture provides two methods by which program space can be accessed during operation: using table instructions to access individual bytes or words anywhere in the program space remapping a portion of the program space into the data space (program space visibility) table instructions allow an application to read or write to small areas of the program memory. this capability makes the method ideal for accessing data tables that need to be updated periodically. it also allows access to all bytes of the program word. the remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. the application can only access the least significant word of the program word. 4.8.1 addressing program space since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. the solution depends on the interface method to be used. for table operations, the 8-bit table page register (tblpag) is used to define a 32k word region within the program space. this is concatenated with a 16-bit ea to arrive at a full 24-bit program space address. in this format, the most significant bit of tblpag is used to determine if the operation occurs in the user memory (tblpag<7> = 0 ) or the configuration memory (tblpag<7> = 1 ). for remapping operations, the 8-bit program space visibility register (psvp ag) is used to define a 16k word page in the program space. when the most significant bit of the ea is 1 , psvpag is concatenated with the lower 15 bits of the ea to form a 23-bit program space address. unlike table operations, this limits remapping operations strictly to the user memory area. table 4-39 and figure 4-9 show how the program ea is created for table operations and remapping accesses from the data ea. here, p<23:0> refers to a program space word, and d<15:0> refers to a data space word. table 4-39: program sp ace address construction access type access space program space address <23> <22:16> <15> <14:1> <0> instruction access (code execution) user 0 pc<22:1> 0 0xx xxxx xxxx xxxx xxxx xxx0 tblrd/tblwt (byte/word read/write) user tblpag<7:0> data ea<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx configuration tblpag<7:0> data ea<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx program space visibility (block remap/read) user 0 psvpag<7:0> data ea<14:0> (1) 0 xxxx xxxx xxx xxxx xxxx xxxx note 1: data ea<15> is always 1 in this case, but is not used in calculating the program space address. bit 15 of the address is psvpag<0>. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 67 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 4-9: data access from pr ogram space addr ess generation 0 program counter 23 bits 1 psvpag 8 bits ea 15 bits program counter (1) select tblpag 8 bits ea 16 bits byte select 0 0 1/0 user/configuration table operations (2) program space visibility (1) space select 24 bits 23 bits (remapping) 1/0 0 note 1: the least significant bit (lsb) of program space addresses is always fixed as 0 to maintain word alignment of data in the program and data spaces. 2: table operations are not required to be word aligned. table read operations are permitted in the configuration memory space. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 68 ? 2007-2012 microchip technology inc. 4.8.2 data access from program memory using table instructions the tblrdl and tblwtl instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. the tblrdh and tblwth instructions are the only me thod to read or write the upper 8 bits of a program space word as data. the pc is incremented by two for each successive 24-bit program word. this allows program memory addresses to directly map to data space addresses. program memory can thus be regarded as two 16-bit- wide word address spaces, residing side by side, each with the same address range. tblrdl and tblwtl access the space that contains the least significant data word. tblrdh and tblwth access the space that contains the upper data byte. two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. both function as either byte or word operations. tblrdl (table read low): - in word mode, this instruction maps the lower word of the program space location (p<15:0>) to a data address (d<15:0>). - in byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. the upper byte is selected when byte select is 1 ; the lower byte is selected when it is 0 . tblrdh (table read high): - in word mode, this instruction maps the entire upper word of a program address (p<23:16>) to a data address. the phantom byte (d<15:8>), is always 0 . - in byte mode, this inst ruction maps the upper or lower byte of the program word to d<7:0> of the data address, in the tblrdl instruc- tion. the data is always 0 when the upper phantom byte is selected (byte select = 1 ). in a similar fashion, two table instructions, tblwth and tblwtl , are used to write individual bytes or words to a program space address. the details of their operation are explained in section 5.0 flash program memory . for all table operations, the area of program memory space to be accessed is determined by the table page register (tblpag). tblpag covers the entire program memory space of the device, including user application and configuration spaces. when tblpag<7> = 0 , the table page is located in the user memory space. when tblpag<7> = 1 , the page is located in configuration space. figure 4-10: accessing program memory with table instructions 0 8 16 23 00000000 00000000 00000000 00000000 phantom byte tblrdh.b (wn<0> = 0 ) tblrdl.w tblrdl.b (wn<0> = 1 ) tblrdl.b (wn<0> = 0 ) 23 15 0 tblpag 02 0x0000000x800000 0x0200000x030000 program space the address for the table operation is determined by the data ea within the page defined by the tblpag register. only read operations are shown; write operations are also valid in the user memory area. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 69 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 4.8.3 reading data from program memory using program space visibility the upper 32 kbytes of data space may optionally be mapped into any 16k word page of the program space. this option provides transparent access to stored constant data from the data space without the need to use special instructions (such as tblrdl/h ). program space access through the data space occurs if the most significant bit of the data space ea is 1 and program space visibility is enabled by setting the psv bit in the core control register (corcon<2>). the location of the program memory space to be mapped into the data space is determined by the program space visibility page register (psvpag). this 8-bit register defines any one of 256 possible pages of 16k words in program space. in effect, psvpag functions as the upper 8 bits of the program memory address, with the 15 bits of the ea functioning as the lower bits. by incrementing the pc by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. data reads to this area ad d a cycle to the instruction being executed, since two program memory fetches are required. although each data space address 0x8000 and higher maps directly into a corresponding program memory address (see figure 4-11 ), only the lower 16 bits of the 24-bit program word are us ed to contain the data. the upper 8 bits of any program space location used as data should be programmed with 1111 1111 or 0000 0000 to force a nop . this prevents possible issues should the area of code ever be accidentally executed. for operations that use psv and are executed outside a repeat loop, the mov and mov.d instructions require one instruction cycle in addition to the specified execution time. all other instructions require two instruction cycles in addition to the specified execution time. for operations that use psv, and are executed inside a repeat loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: execution in th e first iteration execution in the last iteration execution prior to exiting the loop due to an interrupt execution upon re-entering the loop after an interrupt is serviced any other iteration of the repeat loop allows the instruction using psv to access data, to execute in a single cycle. figure 4-11: program space visibility operation note: psv access is temporarily disabled during table reads/writes. 23 15 0 psvpag data space program space 0x00000x8000 0xffff 02 0x0000000x800000 0x0100000x018000 when corcon<2> = 1 and ea<15> = 1 : the data in the page designated by psvpag is mapped into the upper half of the data memory space... data ea<14:0> ...while the lower 15 bits of the ea specify an exact address within the psv area. this corresponds exactly to the same lower 15 bits of the actual program space address. psv area downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 70 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 71 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 5.0 flash program memory the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 devices contain internal flash program memory for storing and executing application code . the memory is readable, writable and erasable during normal operation over the entire v dd range. flash memory can be programmed in two ways: in-circuit serial programming? (icsp?) programming capability run-time self-programming (rtsp) icsp allows any of the following devices, dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04, to be serially programmed while in the end application circuit. this is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: pgecx/pgedx), and three other lines for power (v dd ), ground (v ss ) and master clear (mclr ). this allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. rtsp is accomplished using tblrd (table read) and tblwt (table write) instructions. with rtsp, the user application can write program memory data either in blocks or rows of 64 inst ructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or pages of 512 instructions (1536 bytes) at a time. 5.1 table instructions and flash programming regardless of the method used, all programming of flash memory is done with the table read and table write instructions. these al low direct read and write access to the program memory space from the data memory while the device is in normal operating mode. the 24-bit target address in the program memory is formed using bits <7:0> of the tblpag register and the effective address (ea) from a w register specified in the table instruction, as shown in figure 5-1 . the tblrdl and the tblwtl instructions are used to read or write to bits <15:0> of program memory. tblrdl and tblwtl can access program memory in both word and byte modes. the tblrdh and tblwth instructions are used to read or write to bits <23:16> of program memory. tblrdh and tblwth can also access program memory in word or byte mode. figure 5-1: addressing for table registers note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. flash programming (ds70191) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. 0 program counter 24 bits program counter tblpag reg 8 bits working reg ea 16 bits byte 24-bit ea 0 1/0 select using table instruction using user/configuration space select downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 72 ? 2007-2012 microchip technology inc. 5.2 rtsp operation the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 flash program memory array is organized into rows of 64 instructions or 192 bytes. rtsp allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. table 30-12 shows typical erase and programming times. the 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. the program memory implements holding buffers that can contain 64 instructions of programming data. prior to the actual programming operation, the write data must be loaded into the buffers sequentially. the instruction words loaded must always be from a group of 64 boundary. the basic sequence for rtsp programming is to set up a table pointer, then do a series of tblwt instructions to load the buffers. programming is performed by setting the control bits in the nvmcon register. a total of 64 tblwtl and tblwth instructions are required to load the instructions. all of the table write operat ions are single-word writes (two instruction cycles) because only the buffers are written. a programming cycle is required for programming each row. 5.3 programming operations a complete programming sequence is necessary for programming or erasing the internal flash in rtsp mode. the processor stalls (waits) until the programming operation is finished. the programming time depends on the frc accuracy (see table 30-19 ) and the value of the frc oscillator tuning register (see register 9-4 ). use the formula in equation 5-1 to calculate the minimum and maximum values for the row write time, page erase time and word write cycle time parameters (see table 30-12 ). equation 5-1: programming time for example, if the devic e is operating at +125c, the frc accuracy will be 5%. if the tun<5:0> bits (see register 9-4 ) are set to b111111 , the minimum row write time is equal to equation 5-2 . equation 5-2: minimum row write time the maximum row write time is equal to equation 5-3 . equation 5-3: maximum row write time setting the wr bit (nvmcon<15>) starts the operation, and the wr bit is automatically cleared when the operation is finished. 5.4 control registers two sfrs are used to read and write the program flash memory: nvmcon and nvmkey. the nvmcon register ( register 5-1 ) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. nvmkey ( register 5-2 ) is a write-only register that is used for write protection. to start a programming or erase sequence, the user application must consecu- tively write 0x55 and 0xaa to the nvmkey register. refer to section 5.3 programming operations for further details. 5.5 flash resources many useful resources related to flash memory are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 5.5.1 key resources section 5. flash programming (ds70191) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools t 7.37 mhz frc accuracy () % frc tuning () % --------------------------------------------------------------------------------------------------------------------------- - note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 t rw 11064 cycles 7.37 mhz 10.05 + () 1 0.00375 ? () ------------------------------------------------------------------------------------------------ 1.435 ms = = t rw 11064 cycles 7.37 mhz 10.05 ? () 1 0.00375 ? () ----------------------------------------------------------------------------------------------- - 1.586 ms = = downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 73 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 5.6 flash control registers register 5-1: nvmcon: flash memory control register r/so-0 (1) r/w-0 (1) r/w-0 (1) u-0 u-0 u-0 u-0 u-0 wr wren wrerr bit 15 bit 8 u-0 r/w-0 (1) u-0 u-0 r/w-0 (1) r/w-0 (1) r/w-0 (1) r/w-0 (1) erase n v m o p < 3 : 0 > (2) bit 7 bit 0 legend: so = settable only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 wr: write control bit 1 = initiates a flash memory program or erase operat ion. the operation is self-timed and the bit is cleared by hardware once operation is complete 0 = program or erase operation is complete and inactive bit 14 wren: write enable bit 1 = enable flash program/erase operations 0 = inhibit flash program/erase operations bit 13 wrerr: write sequence error flag bit 1 = an improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the wr bit) 0 = the program or erase operation completed normally bit 12-7 unimplemented: read as 0 bit 6 erase: erase/program enable bit 1 = perform the erase operation specified by nvmop<3:0> on the next wr command 0 = perform the program operation specified by nvmop<3:0> on the next wr command bit 5-4 unimplemented: read as 0 bit 3-0 nvmop<3:0>: nvm operation select bits (2) if erase = 1 : 1111 = memory bulk erase operation 1110 = reserved 1101 = erase general segment 1100 = erase secure segment 1011 = reserved 0011 = no operation 0010 = memory page erase operation 0001 = no operation 0000 = erase a single configuration register byte if erase = 0 : 1111 = no operation 1110 = reserved 1101 = no operation 1100 = no operation 1011 = reserved 0011 = memory word program operation 0010 = no operation 0001 = memory row program operation 0000 = program a single configuration register byte note 1: these bits can only be reset on por. 2: all other combinations of nv mop<3:0> are unimplemented. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 74 ? 2007-2012 microchip technology inc. register 5-2: nvmkey: nonvolatile memory key register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-0 nvmkey<7:0>: key register (w rite-only) bits downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 75 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 5.6.1 programming algorithm for flash program memory programmers can program one row of program flash memory at a time. to do this, it is necessary to erase the 8-row erase page that contains the desired row. the general process is: 1. read eight rows of program memory (512 instructions) and store in data ram. 2. update the program data in ram with the desired new data. 3. erase the block (see example 5-1 ): a) set the nvmop bits (nvmcon<3:0>) to 0010 to configure for block erase. set the erase (nvmcon<6>) and wren (nvmcon<14>) bits. b) write the starting address of the page to be erased into the tblpag and w registers. c) write 0x55 to nvmkey. d) write 0xaa to nvmkey. e) set the wr bit (nvmcon<15>). the erase cycle begins and the cpu stalls for the dura- tion of the erase cycle. when the erase is done, the wr bit is cleared automatically. 4. write the first 64 instructions from data ram into the program memory buffers (see example 5-2 ). 5. write the program block to flash memory: a) set the nvmop bits to 0001 to configure for row programming. clear the erase bit and set the wren bit. b) write 0x55 to nvmkey. c) write 0xaa to nvmkey. d) set the wr bit. the programming cycle begins and the cpu stalls for the duration of the write cycle. when the write to flash mem- ory is done, the wr bit is cleared automatically. 6. repeat steps 4 and 5, using the next available 64 instructions from the block in data ram by incrementing the value in tblpag, until all 512 instructions are written back to flash memory. for protection against accidental operations, the write initiate sequence for nvmkey must be used to allow any erase or program operation to proceed. after the programming command has been executed, the user application must wait for the programming time until programming is complete. the two instructions following the start of the programming sequence should be nop s, as shown in example 5-3 . example 5-1: erasing a program memory page ; set up nvmcon for block erase operation mov #0x4042, w0 ; mov w0, nvmcon ; initialize nvmcon ; init pointer to row to be erased mov #tblpage(prog_addr), w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #tbloffset(prog_addr), w0 ; initialize in-page ea[15:0] pointer tblwtl w0, [w0] ; set base address of erase block disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the erase nop ; command is asserted downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 76 ? 2007-2012 microchip technology inc. example 5-2: loading the write buffers example 5-3: initiating a programming sequence ; set up nvmcon for row programming operations mov #0x4001, w0 ; mov w0, nvmcon ; initialize nvmcon ; set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled mov #0x0000, w0 ; mov w0, tblpag ; initialize pm page boundary sfr mov #0x6000, w0 ; an example program memory address ; perform the tblwt instructions to write the latches ; 0th_program_word mov #low_word_0, w2 ; mov #high_byte_0, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 1st_program_word mov #low_word_1, w2 ; mov #high_byte_1, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 2nd_program_word mov #low_word_2, w2 ; mov #high_byte_2, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch ; 63rd_program_word mov #low_word_31, w2 ; mov #high_byte_31, w3 ; tblwtl w2, [w0] ; write pm low word into program latch tblwth w3, [w0++] ; write pm high byte into program latch disi #5 ; block all interrupts with priority <7 ; for next 5 instructions mov #0x55, w0 mov w0, nvmkey ; write the 55 key mov #0xaa, w1 ; mov w1, nvmkey ; write the aa key bset nvmcon, #wr ; start the erase sequence nop ; insert two nops after the nop ; erase command is asserted downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 77 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 6.0 resets the reset module combines all reset sources and controls the device mast er reset signal, sysrst . the following is a list of device reset sources: por: power-on reset bor: brown-out reset mclr : master clear pin reset swr: reset instruction wdto: watchdog timer reset cm: configuration mismatch reset trapr: trap conflict reset iopuwr: illegal condition device reset - illegal opcode reset - uninitialized w register reset - security reset a simplified block diagram of the reset module is shown in figure 6-1 . any active source of reset will make the sysrst sig- nal active. on system reset, some of the registers associated with the cpu and peripherals are forced to a known reset state and some are unaffected. all types of device reset sets a corresponding status bit in the rcon register to indicate the type of reset (see register 6-1 ). a por clears all the bits, except for the por bit (rcon<0>), that are set. th e user application can set or clear any bit at any time during code execution. the rcon bits only serve as status bits. setting a particular reset status bit in software does not cause a device reset to occur. the rcon register also has other bits associated with the watchdog timer and device power-saving states. the function of these bits is discussed in other sections of this manual. figure 6-1: reset system block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 8. reset (ds70192) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: refer to the specific peripheral section or section 3.0 cpu of this manual for register reset states. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset is meaningful. mclr v dd internal regulator bor sleep or idle reset instruction wdt module glitch filter trap conflict illegal opcode uninitialized w register sysrst v dd rise detect por configuration mismatch downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 78 ? 2007-2012 microchip technology inc. 6.1 reset resources many useful resources related to resets are provided on the main product page of the microchip web site for the devices listed in this dat a sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 6.1.1 key resources section 8. resets (ds70192) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 79 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 6.2 reset control registers register 6-1: rcon: re set control register (1) r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 trapr iopuwr c mv r e g s bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 extr swr swdten (2) wdto sleep idle bor por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 trapr: trap reset flag bit 1 = a trap conflict reset has occurred 0 = a trap conflict reset has not occurred bit 14 iopuwr: illegal opcode or uninitialized w access reset flag bit 1 = an illegal opcode detection, an illegal address mode or uninitialized w register used as an address pointer caused a reset 0 = an illegal opcode or uninitialized w reset has not occurred bit 13-10 unimplemented: read as 0 bit 9 cm: configuration mismatch flag bit 1 = a configuration mismatch reset has occurred 0 = a configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby during sleep bit 1 = voltage regulator is active during sleep 0 = voltage regulator goes into standby mode during sleep bit 7 extr: external reset (mclr ) pin bit 1 = a master clear (pin) reset has occurred 0 = a master clear (pin) reset has not occurred bit 6 swr: software reset (instruction) flag bit 1 = a reset instruction has been executed 0 = a reset instruction has not been executed bit 5 swdten: software enable/disable of wdt bit (2) 1 = wdt is enabled 0 = wdt is disabled bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake-up from sleep flag bit 1 = device has been in sleep mode 0 = device has not been in sleep mode bit 2 idle: wake-up from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is 1 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 80 ? 2007-2012 microchip technology inc. bit 1 bor: brown-out reset flag bit 1 = a brown-out reset has occurred 0 = a brown-out reset has not occurred bit 0 por: power-on reset flag bit 1 = a power-on reset has occurred 0 = a power-on reset has not occurred register 6-1: rcon: re set control register (1) (continued) note 1: all of the reset status bits can be set or cleared in software. setting one of these bits in software does not cause a device reset. 2: if the fwdten configuration bit is 1 (unprogrammed), the wdt is always enabled, regardless of the swdten bit setting. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 81 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 6.3 system reset the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 family of devices have two types of reset: cold reset warm reset a cold reset is the result of a power-on reset (por) or a brown-out reset (bor). on a cold reset, the fnosc configuration bits in the fosc device configuration register selects the device clock source. a warm reset is the result of all other reset sources, including the reset instruction. on warm reset, the device will continue to operate from the current clock source as indicated by the current oscillator selection bits (cosc<2:0>) in the oscillator control register (osccon<14:12>). the device is kept in a reset state until the system power supplies have stabilized at appropriate levels and the oscillator clock is ready. the sequence in which this occurs is shown in figure 6-2 . table 6-1: oscillator delay oscillator mode oscillator startup delay oscillator startup timer pll lock time total delay frc, frcdiv16, frcdivn t oscd t oscd frcpll t oscd t lock t oscd + t lock xt t oscd t ost t oscd + t ost hs t oscd t ost t oscd + t ost e c xtpll t oscd t ost t lock t oscd + t ost + t lock hspll t oscd t ost t lock t oscd + t ost + t lock ecpll t lock t lock sosc t oscd t ost t oscd + t ost lprc t oscd t oscd note 1: t oscd = oscillator start-up delay (1.1 s max for frc, 70 s max for lprc). crystal oscillator start-up times vary with crystal characteristics, load capacitance, etc. 2: t ost = oscillator start-up timer delay (1024 oscillator clock period). for example, t ost = 102.4 s for a 10 mhz crystal and t ost = 32 ms for a 32 khz crystal. 3: t lock = pll lock time (1.5 ms nominal), if pll is enabled. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 82 ? 2007-2012 microchip technology inc. figure 6-2: system reset timing reset run device status v dd v por vbor v bor por bor sysrst t pwrt t por t bor oscillator clock t oscd t ost t lock time fscm t fscm 1 2 3 4 5 6 note 1: por: a por circuit holds the device in reset when the pow er supply is turned on. the por circuit is active until v dd crosses the v por threshold and the delay t por has elapsed. 2: bor: the on-chip voltage regulator has a bor circuit that keeps the device in reset until v dd crosses the v bor threshold and the delay t bor has elapsed. the delay t bor ensures the voltage regulator output becomes stable. 3: pwrt timer: the programmable power-up timer continues to hold the processor in reset for a specific period of time (t pwrt ) after a bor. the delay t pwrt ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. after the delay t pwrt has elapsed, the sysrst becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: oscillator delay: the total delay for the clock to be ready for various clock source se lections are given in table 6-1 . refer to section 9.0 oscillator configuration for more information. 5: when the oscillator cloc k is ready, the processor begins exec ution from location 0x000000. the user application programs a goto instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: the fail-safe clock monitor (fscm), if enabled, begins to monitor the system cl ock when the system clock is ready and the delay t fscm elapsed. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 83 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 6.4 power-on reset (por) a power-on reset (por) circuit ensures the device is reset from power-on. the por circuit is active until v dd crosses the v por threshold and the delay t por has elapsed. the delay t por ensures the internal device bias circuits become stable. the device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the por. refer to section 30.0 electrical characteristics for details. the por status bit (por) in the reset control register (rcon<0>) is set to indicate the power-on reset. 6.4.1 brown-out reset (bor) and power-up timer (pwrt) the on-chip regulator has a brown-out reset (bor) circuit that resets the device when the v dd is too low (v dd < v bor ) for proper device operation. the bor cir- cuit keeps the device in reset until v dd crosses v bor threshold and the delay t bor has elapsed. the delay t bor ensures the voltage re gulator output becomes stable. the bor status bit (bor) in the reset control register (rcon<1>) is set to indicate the brown-out reset. the device will not run at full speed after a bor as the v dd should rise to acceptab le levels for full-speed operation. the pwrt provides power-up time delay (t pwrt ) to ensure that the system power supplies have stabilized at the appropriate levels for full-speed operation before the sysrst is released. the power-up timer delay (t pwrt ) is programmed by the power-on reset timer value select bits (fpwrt<2:0>) in the por configuration register (fpor<2:0>), which provides eight settings (from 0 ms to 128 ms). refer to section 27.0 special features for further details. figure 6-3 shows the typical brown-out scenarios. the reset delay (t bor + t pwrt ) is initiated each time v dd rises above the v bor trip point table 6-2: oscillator delay symbol parameter value v por por threshold 1.8v nominal t por por extension time 30 s maximum v bor bor threshold 2.5v nominal t bor bor extension time 100 s maximum t pwrt programmable power-up time delay 0-128 ms nominal t fscm fail-safe clock monitor delay 900 s maximum note: when the device exits the reset condi- tion (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges, otherwise the device may not function correctly. the user application must ensure that the delay between the time power is first applied, and the time sysrst becomes inactive, is long enough to get all operating parameters within specification. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 84 ? 2007-2012 microchip technology inc. figure 6-3: brown-out situations 6.5 external reset (extr) the external reset is generated by driving the mclr pin low. the mclr pin is a schmitt trigger input with an additional glitch filter. reset pulses that are longer than the minimum pulse-width will generate a reset. refer to section 30.0 electri cal characteristics for minimum pulse-width specifications. the external reset (mclr ) pin (extr) bit in the reset control register (rcon) is set to indicate the mclr reset. 6.5.0.1 external su pervisory circuit many systems have external supervisory circuits that generate reset signals to reset multiple devices in the system. this external reset signal can be directly con- nected to the mclr pin to reset the device when the rest of system is reset. 6.5.0.2 internal supervisory circuit when using the internal power supervisory circuit to reset the device, the external reset pin (mclr ) should be tied directly or resistively to v dd . in this case, the mclr pin will not be used to generate a reset. the external reset pin (mclr ) does not have an internal pull-up and must not be left unconnected. 6.6 software reset instruction (swr) whenever the reset instruction is executed, the device will assert sysrst , placing the device in a special reset state. this reset state will not re- initialize the clock. the clock so urce in effect prior to the reset instruction will remain. sysrst is released at the next instruction cycle, and the reset vector fetch will commence. the software reset (instruction) flag (swr) bit in the reset control (rcon<6>) register is set to indicate the software reset. 6.7 watchdog time-out reset (wdto) whenever a watchdog time-out occurs, the device will asynchronously assert sysrst . the clock source will remain unchanged. a wdt time-out during sleep or idle mode will wake-up the processor, but will not reset the processor. the watchdog timer time-out flag (wdto) bit in the reset control register (rco n<4>) is set to indicate the watchdog reset. refer to section 27.4 watchdog timer (wdt) for more information on watchdog reset. 6.8 trap conflict reset if a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict reset occurs. the hard traps include exceptions of priority level 13 through level 15, inclusive. the address error (level 13) and oscillator error (level 14) traps fall into this category. the trap reset flag (trapr) bit in the reset control register (rcon<15>) is set to indicate the trap conflict reset. refer to section 7.0 interrupt controller for more information on tr ap conflict resets. v dd sysrst v bor v dd sysrst v bor v dd sysrst v bor t bor + t pwrt v dd dips before pwrt expires t bor + t pwrt t bor + t pwrt downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 85 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 6.9 configuration mismatch reset to maintain the integrity of the peripheral pin select control registers, they ar e constantly monitored with shadow registers in hardware. if an unexpected change in any of the registers occur (such as cell dis- turbances caused by esd or other external events), a configuration mismatch reset occurs. the configuration mismatch flag (cm) bit in the reset control register (rcon<9>) is set to indicate the configuration mismatch reset. refer to section 11.0 i/o ports for more information on the configuration mismatch reset. 6.10 illegal condition device reset an illegal condition device reset occurs due to the following sources: illegal opcode reset uninitialized w register reset security reset the illegal opcode or uninitialized w access reset flag (iopuwr) bit in the reset control register (rcon<14>) is set to indicate the illegal condition device reset. 6.10.1 illegal opcode reset a device reset is generated if the device attempts to execute an illegal opcode va lue that is fetched from program memory. the illegal opcode reset function can prevent the device from executing progr am memory sections that are used to store constant data. to take advantage of the illegal opcode reset, use only the lower 16 bits of each program memory section to store the data values. the upper 8 bits should be programmed with 0x3f, which is an illegal opcode value. 6.10.2 uninitialized w register reset any attempts to use the uninitialized w register as an address pointer will reset the device. the w register array (with the exception of w15) is cleared during all resets and is considered unin itialized until written to. 6.10.3 security reset if a program flow change (pfc) or vector flow change (vfc) targets a restricted location in a protected segment (boot and secure segment), that operation will cause a security reset. the pfc occurs when the program counter is reloaded as a result of a call, jump, computed jump, return, return from subroutine, or other form of branch instruction. the vfc occurs when the program counter is reloaded with an interrupt or trap vector. refer to section 27.8 code protection and codeguard? security for more information on security reset. 6.11 using the rcon status bits the user application can read the reset control register (rcon) after any device reset to determine the cause of the reset. table 6-3 provides a summary of the reset flag bit operation. table 6-3: reset flag bit operation note: the configuration mismatch feature and associated reset flag is not available on all devices. note: the status bits in the rcon register should be cleared after they are read so that the next rcon register value after a device reset will be meaningful. flag bit set by: cleared by: trapr (rcon<15>) trap conflict event por, bor iopwr (rcon<14>) illegal opcode or uninitialized w register access or security reset por, bor cm (rcon<9>) configuration mismatch por, bor extr (rcon<7>) mclr reset por swr (rcon<6>) reset instruction por, bor wdto (rcon<4>) wdt time-out pwrsav instruction, clrwdt instruction, por, bor sleep (rcon<3>) pwrsav #sleep instruction por, bor idle (rcon<2>) pwrsav #idle instruction por, bor bor (rcon<1>) por, bor por (rcon<0>) por note: all reset flag bits can be set or cleared by user software. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 86 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 87 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 7.0 interrupt controller the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the dspic33fj32gp302/ 304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 cpu. the interrupt controller has the following features: up to eight processor exceptions and software traps eight user-selectable priority levels interrupt vector table (i vt) with up to 118 vectors a unique vector for each interrupt or exception source fixed priority within a specified user priority level alternate interrupt vector table (aivt) for debug support fixed interrupt entry and return latencies 7.1 interrupt vector table the interrupt vector table (ivt), shown in figure 7-1 , resides in program memory , starting at location 000004h. the ivt contains 126 vectors consisting of eight nonmaskable trap vectors plus up to 118 sources of interrupt. in general, each interrupt source has its own vector. each interrupt vector contains a 24-bit wide address. the value programmed into each interrupt vector location is the starting address of the associated interrupt service routine (isr). interrupt vectors are prioritized in terms of their natural priority. this priority is lin ked to their position in the vector table. lower addresses generally have a higher natural priority. for example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices implement up to 53 unique interrupts and five nonmaskable traps. these are summarized in ta b l e 7 - 1 . 7.1.1 alternate interrupt vector ta b l e the alternate interrupt vector table (aivt) is located after the ivt, as shown in figure 7-1 . access to the aivt is provided by the altivt control bit (intcon2<15>). if the altivt bit is set, all interrupt and exception processes use the alternate vectors instead of the default vector s. the alternate vectors are organized in the same manner as the default vectors. the aivt supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. this feat ure also enables switching between applications for evaluation of different software algorithms at run time. if the aivt is not needed, the aivt should be programmed with the same addresses used in the ivt. 7.2 reset sequence a device reset is not a true exception because the interrupt controller is not involved in the reset process. the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 device clears its registers in response to a reset, which forces the pc to zero. the digital signal controller then begins program execution at location 0x000000. a goto instruction at the reset address can redirect program execution to the appropriate start-up routine. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 32. interrupts (part iii) (ds70214) of the dspic33f/pic24h family reference manual , which is avail- able from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: any unimplemented or unused vector locations in the ivt and aivt should be programmed with the address of a default interrupt handler routine that contains a reset instruction. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 88 ? 2007-2012 microchip technology inc. figure 7-1: dspic33fj32gp302/304, dspic 33fj64gpx02/x04, and dspic33fj128gpx02/ x04 interrupt vector table reset C goto instruction 0x000000 reset C goto address 0x000002 reserved 0x000004 oscillator fail trap vector address error trap vector stack error trap vector math error trap vector dma error trap vector reservedreserved interrupt vector 0 0x000014 interrupt vector 1 ~~ ~ interrupt vector 52 0x00007c interrupt vector 53 0x00007e interrupt vector 54 0x000080 ~~ ~ interrupt vector 116 0x0000fc interrupt vector 117 0x0000fe reserved 0x000100 reserved 0x000102 reserved oscillator fail trap vector address error trap vector stack error trap vector math error trap vector dma error trap vector reservedreserved interrupt vector 0 0x000114 interrupt vector 1 ~~ ~ interrupt vector 52 0x00017c interrupt vector 53 0x00017e interrupt vector 54 0x000180 ~~ ~ interrupt vector 116 interrupt vector 117 0x0001fe start of code 0x000200 decreasing natural order priority interrupt vector table (ivt) (1) alternate interrupt vector table (aivt) (1) note 1: see table 7-1 for the list of implemented interrupt vectors. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 89 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 7-1: interrupt vectors vector number ivt address aivt address interrupt source 0 0x000004 0x000104 reserved 1 0x000006 0x000106 oscillator failure 2 0x000008 0x000108 address error 3 0x00000a 0x00010a stack error 4 0x00000c 0x00010c math error 5 0x00000e 0x00010e dma error 6-7 0x000010-0x000012 0x000110-0x000112 reserved 8 0x000014 0x000114 int0 C external interrupt 0 9 0x000016 0x000116 ic1 C input capture 1 10 0x000018 0x000118 oc1 C output compare 1 11 0x00001a 0x00011a t1 C timer1 12 0x00001c 0x00011c dma0 C dma channel 0 13 0x00001e 0x00011e ic2 C input capture 2 14 0x000020 0x000120 oc2 C output compare 2 15 0x000022 0x000122 t2 C timer2 16 0x000024 0x000124 t3 C timer3 17 0x000026 0x000126 spi1e C spi1 error 18 0x000028 0x000128 spi1 C spi1 transfer done 19 0x00002a 0x00012a u1rx C uart1 receiver 20 0x00002c 0x00012c u1tx C uart1 transmitter 21 0x00002e 0x00012e adc1 C adc 1 22 0x000030 0x000130 dma1 C dma channel 1 23 0x000032 0x000132 reserved 24 0x000034 0x000134 si2c1 C i2c1 slave events 25 0x000036 0x000136 mi2c1 C i2c1 master events 26 0x000038 0x000138 cm C comparator interrupt 27 0x00003a 0x00013a cn C change notification interrupt 28 0x00003c 0x00013c int1 C external interrupt 1 29 0x00003e 0x00013e reserved 30 0x000040 0x000140 ic7 C input capture 7 31 0x000042 0x000142 ic8 C input capture 8 32 0x000044 0x000144 dma2 C dma channel 2 33 0x000046 0x000146 oc3 C output compare 3 34 0x000048 0x000148 oc4 C output compare 4 35 0x00004a 0x00014a t4 C timer4 36 0x00004c 0x00014c t5 C timer5 37 0x00004e 0x00014e int2 C external interrupt 2 38 0x000050 0x000150 u2rx C uart2 receiver 39 0x000052 0x000152 u2tx C uart2 transmitter 40 0x000054 0x000154 spi2e C spi2 error 41 0x000056 0x000156 spi2 C spi2 transfer done 42 0x000058 0x000158 c1rx C ecan1 rx data ready 43 0x00005a 0x00015a c1 C ecan1 event 44 0x00005c 0x00015c dma3 C dma channel 3 45-52 0x00005e-0x00006c 0x00015e-0x00016c reserved 53 0x00006e 0x00016e pmp C parallel master port 54 0x000070 0x000170 dma C dma channel 4 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 90 ? 2007-2012 microchip technology inc. 55-66 0x000072-0x000088 0x000172-0x000188 reserved 67 0x00008a 0x00018a dcie C dci error 68 0x00008c 0x00018c dci C dci transfer done 69 0x00008e 0x00018e dma5 C dma channel 5 70 0x000090 0x000190 rtcc C real time clock 71-72 0x000092-0x000094 0x000192-0x000194 reserved 73 0x000096 0x000196 u1e C uart1 error 74 0x000098 0x000198 u2e C uart2 error 75 0x00009a 0x00019a crc C crc generator interrupt 76 0x00009c 0x00019c dma6 C dma channel 6 77 0x00009e 0x00019e dma7 C dma channel 7 78 0x0000a0 0x0001a0 c1tx C ecan1 tx data request 79-85 0x0000a2-0x0000ae 0x0001a2-0x0001ae reserved 86 0x0000b0 0x0001b0 dac1r C dac1 right data request 87 0x0000b2 0x0001b2 dac1l C dac1 left data request 88-126 0x0000b4-0x0000fe 0x0001b4-0x0001fe reserved table 7-1: interrupt vectors (continued) vector number ivt address aivt address interrupt source downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 91 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 7.3 interrupt control and status registers dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x 04 devices implement a total of 30 registers for the interrupt controller: intcon1 intcon2 ifsx iecx ipcx inttreg 7.3.1 intcon1 and intcon2 global interrupt control functions are controlled from intcon1 and intcon2. intcon1 contains the interrupt nesting disable bit (nstdis) as well as the control and status flags for the processor trap sources. the intcon2 register contro ls the external interrupt request signal behavior and the use of the alternate interrupt vector table. 7.3.2 ifs x the ifs registers maintain all of the interrupt request flags. each source of interrupt has a status bit, which is set by the respective peripherals or external signal and is cleared via software. 7.3.3 iec x the iec registers maintain all of the interrupt enable bits. these control bits are used to individually enable interrupts from the peripherals or external signals. 7.3.4 ipc x the ipc registers are used to set the interrupt priority level for each source of interrupt. each user interrupt source can be assigned to one of eight priority levels. 7.3.5 inttreg the inttreg register contains the associated interrupt vector number and the new cpu interrupt priority level, which are latched into vector number (vecnum<6:0>) and interrupt level bits (ilr<3:0>) in the inttreg register. the new interrupt priority level is the priority of the pending interrupt. the interrupt sources are assigned to the ifsx, iecx and ipcx registers in the sa me sequence that they are listed in ta b l e 7 - 1 . for example, the int0 (external interrupt 0) is shown as having vector number 8 and a natural order priority of 0. thus, the int0if bit is found in ifs0<0>, the int0ie bit in iec0<0>, and the int0ip bits in the first position of ipc0 (ipc0<2:0>). 7.3.6 status/control registers although they are not specific ally part of the interrupt control hardware, two of the cpu control registers contain bits that contro l interrupt functionality. the cpu status register, sr, contains the ipl<2:0> bits (sr<7:5>). these bits indicate the current cpu interrupt priority level. the user software can change the current cpu priority level by writing to the ipl bits. the corcon register contains the ipl3 bit which, together with ipl<2:0>, also indicates the current cpu priority level. ipl3 is a read-only bit so that trap events cannot be masked by the user software. all interrupt registers are described in register 7-1 through register 7-31 . 7.4 interrupts resources many useful resources related to interrupts are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 7.4.1 key resources section 32. interrupts (part iii) (ds70214) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 92 ? 2007-2012 microchip technology inc. 7.5 cpu registers register 7-1: sr: cpu status register (1) r-0 r-0 r/c-0 r/c-0 r-0 r/c-0 r -0 r/w-0 oa ob sa sb oab sab da dc bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ipl<2:0> (2,3) ra n ov z c bit 7 bit 0 legend: c = clear only bit r = readable bit u = unimplemented bit, read as 0 s = set only bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7-5 ipl<2:0>: cpu interrupt priority level status bits (2) 111 = cpu interrupt priority level is 7 (15), user interrupts are disabled 110 = cpu interrupt priority level is 6 (14) 101 = cpu interrupt priority level is 5 (13) 100 = cpu interrupt priority level is 4 (12) 011 = cpu interrupt priority level is 3 (11) 010 = cpu interrupt priority level is 2 (10) 001 = cpu interrupt priority level is 1 (9) 000 = cpu interrupt priority level is 0 (8) note 1: for complete register details, see register 3-1 . 2: the ipl<2:0> bits are concatenated with the ipl<3> bi t (corcon<3>) to form the cpu interrupt priority level. the value in parentheses indicates the ipl if ipl<3> = 1 . user interrupts are disabled when ipl<3> = 1 . 3: the ipl<2:0> status bits are read-onl y when the nstdis bit (intcon1<15>) = 1 . register 7-2: corcon: core control register (1) u-0 u-0 u-0 r/w-0 r/w-0 r-0 r-0 r-0 u se d t d l < 2 : 0 > bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/c-0 r/w-0 r/w-0 r/w-0 sata satb satdw accsat ipl3 (2) psv rnd if bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknow n u = unimplemented bit, read as 0 bit 3 ipl3: cpu interrupt priority level status bit 3 (2) 1 = cpu interrupt priority level is greater than 7 0 = cpu interrupt priority level is 7 or less note 1: for complete register details, see register 3-2 . 2: the ipl3 bit is concatenated with t he ipl<2:0> bits (sr<7:5>) to form the cpu interrupt priority level. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 93 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-3: intcon1: interrupt control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nstdis ovaerr ovberr covaerr covberr ovate ovbte covte bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 sftacerr div0err dmacerr matherr addrerr stkerr oscfail bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 nstdis: interrupt nesting disable bit 1 = interrupt nesting is disabled 0 = interrupt nesting is enabled bit 14 ovaerr: accumulator a overflow trap flag bit 1 = trap was caused by overflow of accumulator a 0 = trap was not caused by overflow of accumulator a bit 13 ovberr: accumulator b overflow trap flag bit 1 = trap was caused by overflow of accumulator b 0 = trap was not caused by overflow of accumulator b bit 12 covaerr: accumulator a catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator a 0 = trap was not caused by catastrophic overflow of accumulator a bit 11 covberr: accumulator b catastrophic overflow trap flag bit 1 = trap was caused by catastrophic overflow of accumulator b 0 = trap was not caused by catastrophic overflow of accumulator b bit 10 ovate: accumulator a overflow trap enable bit 1 = trap overflow of accumulator a 0 = trap disabled bit 9 ovbte: accumulator b overflow trap enable bit 1 = trap overflow of accumulator b 0 = trap disabled bit 8 covte: catastrophic overflow trap enable bit 1 = trap on catastrophic overflow of accumulator a or b enabled 0 = trap disabled bit 7 sftacerr: shift accumulator error status bit 1 = math error trap was caused by an invalid a ccumulator shift 0 = math error trap was not caused by an invalid accumulator shift bit 6 div0err: arithmetic error status bit 1 = math error trap was caused by a divide by zero 0 = math error trap was not caused by a divide by zero bit 5 dmacerr: dma controller error status bit 1 = dma controller error trap has occurred 0 = dma controller error trap has not occurred bit 4 matherr: arithmetic error status bit 1 = math error trap has occurred 0 = math error trap has not occurred downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 94 ? 2007-2012 microchip technology inc. bit 3 addrerr: address error trap status bit 1 = address error trap has occurred 0 = address error trap has not occurred bit 2 stkerr: stack error trap status bit 1 = stack error trap has occurred 0 = stack error trap has not occurred bit 1 oscfail: oscillator failure trap status bit 1 = oscillator failure trap has occurred 0 = oscillator failure trap has not occurred bit 0 unimplemented: read as 0 register 7-3: intcon1: interrupt control register 1 (continued) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 95 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-4: intcon2: interrupt control register 2 r/w-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 altivt disi bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 int2ep int1ep int0ep bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 altivt: enable alternate interrupt vector table bit 1 = use alternate vector table 0 = use standard (default) vector table bit 14 disi: disi instruction status bit 1 = disi instruction is active 0 = disi instruction is not active bit 13-3 unimplemented: read as 0 bit 2 int2ep: external interrupt 2 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 1 int1ep: external interrupt 1 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge bit 0 int0ep: external interrupt 0 edge detect polarity select bit 1 = interrupt on negative edge 0 = interrupt on positive edge downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 96 ? 2007-2012 microchip technology inc. register 7-5: ifs0: interrupt flag status register 0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dma1if ad1if u1txif u1rxif spi1if spi1eif t3if bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t2if oc2if ic2if dma0if t1if oc1if ic1if int0if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 dma1if: dma channel 1 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 ad1if: adc1 conversion complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 u1txif: uart1 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 u1rxif: uart1 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 spi1if: spi1 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 spi1eif: spi1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 t3if: timer3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 t2if: timer2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 oc2if: output compare channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 ic2if: input capture channel 2 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 dma0if: dma channel 0 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 t1if: timer1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 97 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 2 oc1if: output compare channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 ic1if: input capture channel 1 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 int0if: external interrupt 0 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-5: ifs0: interrupt flag status register 0 (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 98 ? 2007-2012 microchip technology inc. register 7-6: ifs1: interrupt flag status register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u2txif u2rxif int2if t5if t4if oc4if oc3if dma2if bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic8if ic7if int1if cnif cmif mi2c1if si2c1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 u2txif: uart2 transmitter interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 u2rxif: uart2 receiver interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 int2if: external interrupt 2 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 t5if: timer5 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 t4if: timer4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10 oc4if: output compare channel 4 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 9 oc3if: output compare channel 3 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 8 dma2if: dma channel 2 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 7 ic8if: input capture channel 8 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 ic7if: input capture channel 7 interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 unimplemented: read as 0 bit 4 int1if: external interrupt 1 flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 cnif: input change notification interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 99 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 2 cmif: comparator interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 mi2c1if: i2c1 master events in terrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 si2c1if: i2c1 slave events interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred register 7-6: ifs1: interrupt flag status register 1 (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 100 ? 2007-2012 microchip technology inc. register 7-7: ifs2: interrupt flag status register 2 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 d m a 4 i fp m p i f bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 d m a 3 i fc 1 i f (1) c1rxif (1) spi2if spi2eif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 dma4if: dma channel 4 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 pmpif: parallel master port interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12-5 unimplemented: read as 0 bit 4 dma3if: dma channel 3 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 c1if: ecan1 event interrupt flag status bit (1) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 c1rxif: ecan1 receive data ready interrupt flag status bit (1) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 spi2if: spi2 event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 spi2eif: spi2 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred note 1: interrupts are disabled on devices without ecan? modules. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 101 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-8: ifs3: interrupt flag status register 3 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 rtcif dma5if dciif dcieif bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 rtcif: real-time clock and calendar interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13 dma5if: dma channel 5 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 12 dciif: dci event interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 11 dcieif: dci error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 10-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 102 ? 2007-2012 microchip technology inc. register 7-9: ifs4: interrupt flag status register 4 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 dac1lif (2) dac1rif (2) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 c 1 t x i f (1) dma7if dma6if crcif u2eif u1eif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 dac1lif: dac left channel interrupt flag status bit (2) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 14 dac1rif: dac right channel interrupt flag status bit (2) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 13-7 unimplemented: read as 0 bit 6 c1txif: ecan1 transmit data request interrupt flag status bit (1) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 dma7if: dma channel 7 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 dma6if: dma channel 6 data transfer complete interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 3 crcif: crc generator interru pt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 u2eif: uart2 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 u1eif: uart1 error interrupt flag status bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 unimplemented: read as 0 note 1: interrupts are disabled on devices without ecan? modules. 2: interrupts are disabled on devices without audio dac modules. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 103 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-10: iec0: interrupt enable control register 0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dma1ie ad1ie u1txie u1rxie spi1ie spi1eie t3ie bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t2ie oc2ie ic2ie dma0ie t1ie oc1ie ic1ie int0ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 dma1ie: dma channel 1 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13 ad1ie: adc1 conversion complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 u1txie: uart1 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 u1rxie: uart1 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 spi1ie: spi1 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 spi1eie: spi1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 t3ie: timer3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 t2ie: timer2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 oc2ie: output compare channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 ic2ie: input capture channel 2 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 dma0ie: dma channel 0 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 t1ie: timer1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 104 ? 2007-2012 microchip technology inc. bit 2 oc1ie: output compare channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 ic1ie: input capture channel 1 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 int0ie: external interrupt 0 flag status bit 1 = interrupt request enabled 0 = interrupt request not enabled register 7-10: iec0: interrupt enable control register 0 (continued) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 105 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-11: iec1: interrupt enable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u2txie u2rxie int2ie t5ie t4ie oc4ie oc3ie dma2ie bit 15 bit 8 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ic8ie ic7ie int1ie cnie cmie mi2c1ie si2c1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 u2txie: uart2 transmitter interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 14 u2rxie: uart2 receiver interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13 int2ie: external interrupt 2 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 t5ie: timer5 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 t4ie: timer4 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10 oc4ie: output compare channel 4 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 9 oc3ie: output compare channel 3 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 8 dma2ie: dma channel 2 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 7 ic8ie: input capture channel 8 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 ic7ie: input capture channel 7 interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 unimplemented: read as 0 bit 4 int1ie: external interrupt 1 enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 cnie: input change notification interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 106 ? 2007-2012 microchip technology inc. bit 2 cmie: comparator interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 mi2c1ie: i2c1 master events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 si2c1ie: i2c1 slave events interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled register 7-11: iec1: interrupt enable control register 1 (continued) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 107 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-12: iec2: interrupt enable control register 2 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 d m a 4 i ep m p i e bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 d m a 3 i ec 1 i e (1) c1rxie (1) spi2ie spi2eie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 dma4ie: dma channel 4 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13 pmpie: parallel master port interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12-5 unimplemented: read as 0 bit 4 dma3ie: dma channel 3 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request has enabled bit 3 c1ie: ecan1 event interrupt enable bit (1) 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 c1rxie: ecan1 receive data ready interrupt enable bit (1) 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 spi2ie: spi2 event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 spi2eie: spi2 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled note 1: interrupts are disabled on devices without ecan? modules. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 108 ? 2007-2012 microchip technology inc. register 7-13: iec3: interrupt enable control register 3 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 rtcie dma5ie dciie dcieie bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 rtcie: real-time clock and calendar interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 13 dma5ie: dma channel 5 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 12 dciie: dci event interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 11 dcieie: dci error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 10-0 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 109 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-14: iec4: interrupt enable control register 4 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 dac1lie (2) dac1rie (2) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 c 1 t x i e (1) dma7ie dma6ie crcie u2eie u1eie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 dac1lie: dac left channel interrupt enable bit (2) 1 = interrupt request enabled 0 = interrupt request not enabled bit 14 dac1rie: dac right channel interrupt enable bit (2) 1 = interrupt request enabled 0 = interrupt request not enabled bit 13-7 unimplemented: read as 0 bit 6 c1txie: ecan1 transmit data request interrupt enable bit (1) 1 = interrupt request occurred 0 = interrupt request not occurred bit 5 dma7ie: dma channel 7 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 dma6ie: dma channel 6 data transfer complete interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 3 crcie: crc generator interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 u2eie: uart2 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 u1eie: uart1 error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 unimplemented: read as 0 note 1: interrupts are disabled on devices without ecan? modules. 2: interrupts are disabled on devices without audio dac modules. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 110 ? 2007-2012 microchip technology inc. register 7-15: ipc0: interrupt priority control register 0 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 t1ip<2:0> o c 1 i p < 2 : 0 > bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 i c 1 i p < 2 : 0 > int0ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 t1ip<2:0>: timer1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 oc1ip<2:0>: output compare channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 ic1ip<2:0>: input capture channel 1 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 int0ip<2:0>: external interrupt 0 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 111 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-16: ipc1: interrupt priority control register 1 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 t2ip<2:0> o c 2 i p < 2 : 0 > bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 i c 2 i p < 2 : 0 > d m a 0 i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 t2ip<2:0>: timer2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 oc2ip<2:0>: output compare channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 ic2ip<2:0>: input capture channel 2 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 dma0ip<2:0>: dma channel 0 data transfer co mplete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 112 ? 2007-2012 microchip technology inc. register 7-17: ipc2: interrupt priority control register 2 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 u1rxip<2:0> spi1ip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 spi1eip<2:0> t3ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 u1rxip<2:0>: uart1 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 spi1ip<2:0>: spi1 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 spi1eip<2:0>: spi1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 t3ip<2:0>: timer3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 113 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-18: ipc3: interrupt priority control register 3 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 d m a 1 i p < 2 : 0 > bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 a d 1 i p < 2 : 0 > u1txip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 dma1ip<2:0>: dma channel 1 data transfer co mplete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 ad1ip<2:0>: adc1 conversion complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 u1txip<2:0>: uart1 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 114 ? 2007-2012 microchip technology inc. register 7-19: ipc4: interrupt priority control register 4 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 cnip<2:0> cmip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 mi2c1ip<2:0> si2c1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 cnip<2:0>: change notification interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 cmip<2:0>: comparator interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 mi2c1ip<2:0>: i2c1 master events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 si2c1ip<2:0>: i2c1 slave events interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 115 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-20: ipc5: interrupt priority control register 5 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 i c 8 i p < 2 : 0 > ic7ip<2:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 int1ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 ic8ip<2:0>: input capture channel 8 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 ic7ip<2:0>: input capture channel 7 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-3 unimplemented: read as 0 bit 2-0 int1ip<2:0>: external interrupt 1 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 116 ? 2007-2012 microchip technology inc. register 7-21: ipc6: interrupt priority control register 6 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 t4ip<2:0> o c 4 i p < 2 : 0 > bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 oc3ip<2:0> d m a 2 i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 t4ip<2:0>: timer4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 oc4ip<2:0>: output compare channel 4 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 oc3ip<2:0>: output compare channel 3 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 dma2ip<2:0>: dma channel 2 data transfer complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 117 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-22: ipc7: interrupt priority control register 7 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 u2txip<2:0> u2rxip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 int2ip<2:0> t5ip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 u2txip<2:0>: uart2 transmitter interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 u2rxip<2:0>: uart2 receiver interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 int2ip<2:0>: external interrupt 2 priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 t5ip<2:0>: timer5 interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 118 ? 2007-2012 microchip technology inc. register 7-23: ipc8: interrupt priority control register 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 c1ip<2:0> (1) c1rxip<2:0> (1) bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 spi2ip<2:0> spi2eip<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 c1ip<2:0>: ecan1 event interrupt priority bits (1) 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 c1rxip<2:0>: ecan1 receive data ready interrupt priority bits (1) 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 spi2ip<2:0>: spi2 event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 spi2eip<2:0>: spi2 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled note 1: interrupts are disabled on devices without ecan? modules. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 119 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-24: ipc9: interrupt priority control register 9 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 d m a 3 i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 dma3ip<2:0>: dma channel 3 data transfer co mplete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 120 ? 2007-2012 microchip technology inc. register 7-25: ipc11: interrupt priority control register 11 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 d m a 4 i p < 2 : 0 > bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 p m p i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 dma4ip<2:0>: dma channel 4 data transfer complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 pmpip<2:0>: parallel master port interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 121 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-26: ipc14: interrupt priority control register 14 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 dcieip<2:0> bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 dcieip<2:0>: dci error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 122 ? 2007-2012 microchip technology inc. register 7-27: ipc15: interrupt priority control register 15 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 rtcip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 dma5ip<2:0> d c i i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 rtcip<2:0>: real-time clock and calendar interrupt flag status bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 dma5ip<2:0>: dma channel 5 data transfer complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 dciip<2:0>: dci event interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 123 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-28: ipc16: interrupt priority control register 16 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 crcip<2:0> u2eip<2:0> bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u 1 e i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 crcip<2:0>: crc generator e rror interrupt flag priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 u2eip<2:0>: uart2 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 u1eip<2:0>: uart1 error interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3-0 unimplemented: read as 0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 124 ? 2007-2012 microchip technology inc. register 7-29: ipc17: interrupt priority control register 17 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-0 c1txip<2:0> (1) bit 15 bit 8 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-1 r/w-0 r/w-0 dma7ip<2:0> d m a 6 i p < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 c1txip<2:0>: ecan1 transmit data request interrupt priority bits (1) 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7 unimplemented: read as 0 bit 6-4 dma7ip<2:0>: dma channel 7 data transfer complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 3 unimplemented: read as 0 bit 2-0 dma6ip<2:0>: dma channel 6 data transfer complete interrupt priority bits 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled note 1: interrupts are disabled on devices without ecan? modules. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 125 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 7-30: ipc19: interrupt priority control register 19 u-0 r/w-1 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 dac1lip<2:0> (1) dac1rip<2:0> (1) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 dac1lip<2:0>: dac left channel interrupt flag status bit (1) 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 11 unimplemented: read as 0 bit 10-8 dac1rip<2:0>: dac right channel interrupt flag status bit (1) 111 = interrupt is priority 7 (highest priority interrupt) 001 = interrupt is priority 1 000 = interrupt source is disabled bit 7-0 unimplemented: read as 0 note 1: interrupts are disabled on devices without audio dac modules. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 126 ? 2007-2012 microchip technology inc. register 7-31: inttreg: interrup t control and status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 i l r < 3 : 0 > bit 15 bit 8 u-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 vecnum<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 ilr<3:0>: new cpu interrupt priority level bits 1111 = cpu interrupt priority level is 15 0001 = cpu interrupt priority level is 1 0000 = cpu interrupt priority level is 0 bit 7 unimplemented: read as 0 bit 6-0 vecnum<6:0>: vector number of pending interrupt bits 0111111 = interrupt vector pending is number 135 0000001 = interrupt vector pending is number 9 0000000 = interrupt vector pending is number 8 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 127 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 7.6 interrupt setup procedures 7.6.1 initialization to configure an interrupt source at initialization: 1. set the nstdis bit (intcon1<15>) if nested interrupts are not desired. 2. select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate ipcx register. the priority level depends on the specific application and type of interrupt source. if multiple priority levels are not desired, the ipcx register control bits for all enabled interrupt sources can be programmed to the same non-zero value. 3. clear the interrupt flag status bit associated with the peripheral in the associated ifsx register. 4. enable the interrupt source by setting the inter- rupt enable control bit associated with the source in the appropriate iecx register. 7.6.2 interrupt service routine the method used to declare an isr and initialize the ivt with the correct vector address depends on the programming language (c or assembler) and the language development tool suite used to develop the application. in general, the user application must clear the interrupt flag in the appropriate ifsx register for the source of interrupt that the isr handles. otherwise, the program re-enters the isr immediatel y after exiting the routine. if the isr is coded in a ssembly language, it must be terminated using a retfie instruction to unstack the saved pc value, srl value and old cpu priority level. 7.6.3 trap service routine a trap service routine (tsr) is coded like an isr, except that the appropriate trap status flag in the intcon1 register must be cleared to avoid re-entry into the tsr. 7.6.4 interrupt disable all user interrupts can be disabled using this procedure: 1. push the current sr value onto the software stack using the push instruction. 2. force the cpu to priority level 7 by inclusive oring the value oeh with srl. to enable user interrupts, the pop instruction can be used to restore the previous sr value. the disi instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. level 7 interrupt sources are not disabled by the disi instruction. note: at a device reset, the ipcx registers are initialized such that all user interrupt sources are assigned to priority level 4. note: only user interrupts with a priority level of 7 or lower can be disabled. trap sources (level 8-level 15) cannot be disabled. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 128 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 129 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 8.0 direct memory access (dma) direct memory access (dma) is a very efficient mechanism of copying data between peripheral sfrs (e.g., uart receive register, input capture 1 buffer), and buffers or variables stored in ram, with minimal cpu intervention. the dma controller can automatically copy entire blocks of data without requiring the user software to read or write the peripheral special function registers (sfrs) every time a peripheral interrupt occurs. the dma controller uses a dedicated bus for data transfers and therefore, does not steal cycles from the code execut ion flow of the cpu. to exploit the dma capability, the corresponding user buffers or variables must be located in dma ram. the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128g px02/x04 peripherals that can utilize dma are listed in table 8-1 . note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 38. direct memory access (dma) (part iii) (ds70215) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. table 8-1: dma channel to peripheral associations peripheral to dma association dmaxreq register irqsel<6:0> bits dmaxpad register values to read from peripheral dmaxpad register values to write to peripheral int0 C external interrupt 0 0000000 ic1 C input capture 1 0000001 0x0140 (ic1buf) oc1 C output compare 1 data 0000010 0x0182 (oc1r) oc1 C output compare 1 secondary data 0000010 0x0180 (oc1rs) ic2 C input capture 2 0000101 0x0144 (ic2buf) oc2 C output compare 2 data 0000110 0x0188 (oc2r) oc2 C output compare 2 secondary data 0000110 0x0186 (oc2rs) tmr2 C timer2 0000111 tmr3 C timer3 0001000 spi1 C transfer done 0001010 0x0248 (spi1buf) 0x0248 (spi1buf) uart1rx C uart1 receiver 0001011 0x0226 (u1rxreg) uart1tx C uart1 transmitter 0001100 0x0224 (u1txreg) adc1 C adc1 convert done 0001101 0x0300 (adc1buf0) uart2rx C uart2 receiver 0011110 0x0236 (u2rxreg) uart2tx C uart2 transmitter 0011111 0x0234 (u2txreg) spi2 C transfer done 0100001 0x0268 (spi2buf) 0x0268 (spi2buf) ecan1 C rx data ready 0100010 0x0440 (c1rxd) pmp C master data transfer 0101101 0x0608 (pmdin1) 0x0608 (pmdin1) ecan1 C tx data request 1000110 0x0442 (c1txd) dci C codec transfer done 0111100 0x0290 (rxbuf0) 0x0298 (txbuf0) dac1 C right data output 1001110 0x03f6 (dac1rdat) dac2 C left data output 1001111 0x03f8 (dac1ldat) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 130 ? 2007-2012 microchip technology inc. the dma controller featur es eight identical data transfer channels. each channel has its own set of control and status registers. each dma chan nel can be configured to copy data either from buffers stored in dual port dma ram to peripheral sfrs, or from peripheral sfrs to buffers in dma ram. the dma controller support s the following features: eight dma channels register indirect with post-increment addressing mode register indirect without post-increment addressing mode peripheral indirect addressing mode (peripheral generates destination address) cpu interrupt after half or full block transfer complete byte or word transfers fixed priority channel arbitration manual (software) or automatic (peripheral dma requests) transfer initiation one-shot or auto-repeat block transfer modes ping-pong mode (automatic switch between two dpsram start addresses after each block trans- fer complete) dma request for each channel can be selected from any supported interrupt source debug support features for each dma channel, a dma interrupt request is generated when a block transfer is complete. alternatively, an interrupt can be generated when half of the block has been filled. figure 8-1: top level system architecture using a dedicated transaction bus cpu sram dma ram cpu peripheral ds bus peripheral 3 dma peripheral non-dma sram x-bus port 2 port 1 peripheral 1 dma ready peripheral 2 dma ready ready ready dma ds bus cpu dma cpu dma cpu dma peripheral indirect address dma control dma controller dma channels note: cpu and dma address buses are not shown for clarity. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 131 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 8.1 dma resources many useful resources related to the cpu are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 8.1.1 key resources section 38. direct memory access (dma) (part iii) (ds70215) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools 8.2 dmac registers each dmac channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7) contains the following registers: a 16-bit dma channel control register (dmaxcon) a 16-bit dma channel irq select register (dmaxreq) a 16-bit dma ram primary start address register (dmaxsta) a 16-bit dma ram secondary start address register (dmaxstb) a 16-bit dma peripheral address register (dmaxpad) a 10-bit dma transfer count register (dmaxcnt) an additional pair of stat us registers, dmacs0 and dmacs1, are common to all dmac channels. dmacs0 contains the dma ram and sfr write colli- sion flags, xwcolx and pwcolx, respectively. dmacs1 indicates dma channel and ping-pong mode status. the dmaxcon, dmaxreq, dmaxpad and dmaxcnt are all conventional read/write registers. reads of dmaxsta or dmaxstb reads the contents of the dma ram address register. writes to dmax- sta or dmaxstb write to th e registers. this allows the user to determine the dma buffer pointer value (address) at any time. the interrupt flags (dmaxif) are located in an ifsx register in the interrupt controller. the corresponding interrupt enable control bits (dmaxie) are located in an iecx register in the interrupt controller, and the cor- responding interrupt priority control bits (dmaxip) are located in an ipcx register in the interrupt controller. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 132 ? 2007-2012 microchip technology inc. 8.3 dma control registers register 8-1: dmaxcon: dma channel x control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 chen size dir half nullw bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 a m o d e < 1 : 0 > mode<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 chen: channel enable bit 1 = channel enabled 0 = channel disabled bit 14 size: data transfer size bit 1 = byte 0 = word bit 13 dir : transfer direction bit (source/destination bus select) 1 = read from dma ram address, write to peripheral address 0 = read from peripheral address, write to dma ram address bit 12 half: early block transfer comple te interrupt select bit 1 = initiate block transfer complete interrupt when half of the data has been moved 0 = initiate block transfer co mplete interrupt when all of the data has been moved bit 11 nullw: null data peripheral write mode select bit 1 = null data write to peripheral in addition to dma ram write (dir bit must also be clear) 0 = normal operation bit 10-6 unimplemented: read as 0 bit 5-4 amode<1:0>: dma channel operating mode select bits 11 = reserved (acts as peripheral indirect addressing mode) 10 = peripheral indirect addressing mode 01 = register indirect without post-increment mode 00 = register indirect with post-increment mode bit 3-2 unimplemented: read as 0 bit 1-0 mode<1:0>: dma channel operating mode select bits 11 = one-shot, ping-pong modes enabled (one bl ock transfer from/to each dma ram buffer) 10 = continuous, ping-pong modes enabled 01 = one-shot, ping-pong modes disabled 00 = continuous, ping-pong modes disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 133 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 8-2: dmaxreq: dma channel x irq select register r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 force (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irqsel6<6:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 force: force dma transfer bit (1) 1 = force a single dma transfer (manual mode) 0 = automatic dma transfer initiation by dma request bit 14-7 unimplemented: read as 0 bit 6-0 irqsel<6:0>: dma peripheral irq number select bits (2) 1111111 = dmairq127 selected to be channel dmareq .. . 0000000 = dmairq0 selected to be channel dmareq note 1: the force bit cannot be cleared by the user. the fo rce bit is cleared by hardware when the forced dma transfer is complete. 2: refer to ta b l e 7 - 1 for a complete listing of irq numbers for all interrupt sources. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 134 ? 2007-2012 microchip technology inc. register 8-3: dmaxsta: dma channel x ram start address register a (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sta<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sta<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 sta<15:0>: primary dma ram start address bits (source or destination) note 1: a read of this address register returns the current c ontents of the dma ram address register, not the con- tents written to sta<15:0>. if the channel is enabled (i.e ., active), writes to this register may result in unpredictable behavior of the dma channel and should be avoided. register 8-4: dmaxstb: dma channel x ram start address register b (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stb<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stb<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 stb<15:0>: secondary dma ram start address bits (source or destination) note 1: a read of this address register returns the current c ontents of the dma ram address register, not the con- tents written to stb<15:0>. if the channel is enabled (i.e ., active), writes to this register may result in unpredictable behavior of the dma channel and should be avoided. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 135 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 8-5: dmaxpad: dma channel x peripheral address register (1) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pad<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pad<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 pad<15:0>: peripheral address register bits note 1: if the channel is enabled (i.e., active), writes to th is register may result in unpredictable behavior of the dma channel and should be avoided. register 8-6: dmaxcnt: dma channel x transfer count register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 cnt<9:8> (2) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9-0 cnt<9:0>: dma transfer count register bits (2) note 1: if the channel is enabled (i.e., active), writes to th is register may result in unpredictable behavior of the dma channel and should be avoided. 2: number of dma transfers = cnt<9:0> + 1. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 136 ? 2007-2012 microchip technology inc. register 8-7: dmacs0: dma controller status register 0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 pwcol7 pwcol6 pwco l5 pwcol4 pwcol3 pwcol2 pwcol1 pwcol0 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 xwcol7 xwcol6 xwco l5 xwcol4 xwcol3 xwcol2 xwcol1 xwcol0 bit 7 bit 0 legend: c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pwcol7: channel 7 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 14 pwcol6: channel 6 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 13 pwcol5: channel 5 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 12 pwcol4: channel 4 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 11 pwcol3: channel 3 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 10 pwcol2: channel 2 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 9 pwcol1: channel 1 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 8 pwcol0: channel 0 peripheral write collision flag bit 1 = write collision detected 0 = no write collision detected bit 7 xwcol7: channel 7 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 6 xwcol6: channel 6 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 5 xwcol5: channel 5 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 4 xwcol4: channel 4 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 137 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 3 xwcol3: channel 3 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 2 xwcol2: channel 2 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 1 xwcol1: channel 1 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected bit 0 xwcol0: channel 0 dma ram write collision flag bit 1 = write collision detected 0 = no write collision detected register 8-7: dmacs0: dma controller status register 0 (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 138 ? 2007-2012 microchip technology inc. register 8-8: dmacs1: dma controller status register 1 u-0 u-0 u-0 u-0 r-1 r-1 r-1 r-1 lstch<3:0> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 lstch<3:0>: last dma channel active bits 1111 = no dma transfer has occurred since system reset 1110 - 1000 = reserved 0111 = last data transfer was by dma channel 7 0110 = last data transfer was by dma channel 6 0101 = last data transfer was by dma channel 5 0100 = last data transfer was by dma channel 4 0011 = last data transfer was by dma channel 3 0010 = last data transfer was by dma channel 2 0001 = last data transfer was by dma channel 1 0000 = last data transfer was by dma channel 0 bit 7 ppst7: channel 7 ping-pong mode status flag bit 1 = dma7stb register selected 0 = dma7sta register selected bit 6 ppst6: channel 6 ping-pong mode status flag bit 1 = dma6stb register selected 0 = dma6sta register selected bit 5 ppst5: channel 5 ping-pong mode status flag bit 1 = dma5stb register selected 0 = dma5sta register selected bit 4 ppst4: channel 4 ping-pong mode status flag bit 1 = dma4stb register selected 0 = dma4sta register selected bit 3 ppst3: channel 3 ping-pong mode status flag bit 1 = dma3stb register selected 0 = dma3sta register selected bit 2 ppst2: channel 2 ping-pong mode status flag bit 1 = dma2stb register selected 0 = dma2sta register selected bit 1 ppst1: channel 1 ping-pong mode status flag bit 1 = dma1stb register selected 0 = dma1sta register selected bit 0 ppst0: channel 0 ping-pong mode status flag bit 1 = dma0stb register selected 0 = dma0sta register selected downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 139 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 8-9: dsadr : most recent dma ram address r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dsadr<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dsadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 dsadr<15:0>: most recent dma ram address accessed by dma controller bits downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 140 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 141 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 9.0 oscillator configuration the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx0 2/x04 oscillator system provides: external and internal oscillator options as clock sources an on-chip phase-locked loop (pll) to scale the internal operating frequency to the required system clock frequency an internal frc oscillator that can also be used with the pll, thereby allowing full-speed operation without any external clock generation hardware clock switching between various clock sources programmable clock postscaler for system power savings a fail-safe clock monitor (fscm) that detects clock failure and takes fail-safe measures an oscillator control register (osccon) non-volatile configuration bits for main oscillator selection an auxiliary crystal oscillator for audio dac a simplified diagram of the oscillator system is shown in figure 9-1 . figure 9-1: dspic33fj32gp302/304, dspi c33fj64gpx02/x04, and dspic33fj128gpx02/ x04 oscillator system diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 39. oscillator (part iii) (ds70216) of the dspic33f/ pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. secondary oscillator lposcen sosco sosci timer1 xtpll, hspll, xt, hs, ec frcdiv<2:0> wdt, pwrt, fscm frcdivn sosc frcdiv16 ecpll, frcpll nosc<2:0> fnosc<2:0> reset frc oscillator lprc oscillator doze<2:0> s3 s1 s2 s1/s3 s7 s6 frc lprc s0 s5s4 16 clock switch s7 clock fail 2 tun<5:0> pll f cy (3) f osc frcdiv doze note 1: see figure 9-2 for pll details. 2: if the oscillator is used with xt or hs modes, an extended parallel resistor with the value of 1 m must be connected. 3: the term f p refers to the clock source for all the peripherals, while f cy refers to the clock source for the cpu. throughout this document f cy and f p are used interchangeably, except in the case of doze mode. f p and f cy will be different when doze mode is used in any ratio ot her than 1:1, which is the default. n aclk poscclk auxiliary oscillator selack apstsclr<2:0> dac f osc (1) aoscclk aoscmd<1:0> asrcsel f osc (1) poscclk osc2 osc1 primary oscillator r (2) poscmd<1:0> f p (3) 3.5 mhz aux_osc_f in 10 mhz 10 0 1 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 142 ? 2007-2012 microchip technology inc. 9.1 cpu clocking system the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 devices provide seven system clock options: fast rc (frc) oscillator frc oscillator with phase-locked loop (pll) primary (xt, hs or ec) oscillator primary oscillator with pll secondary (lp) oscillator low-power rc (lprc) oscillator frc oscillator with postscaler 9.1.1 system clock sources the fast rc (frc) internal oscillator runs at a nominal frequency of 7.37 mhz. user software can tune the frc frequency. user software can optionally specify a factor (ranging from 1:2 to 1:256) by which the frc clock frequency is divided. th is factor is selected using the frcdiv<2:0> bits (clkdiv<10:8>). the primary oscillator can use one of the following as its clock source: crystal (xt): crystals a nd ceramic resonators in the range of 3 mhz to 10 mhz. the crystal is connected to the osc1 and osc2 pins. high-speed crystal (hs): crystals in the range of 10 mhz to 40 mhz. the crystal is connected to the osc1 and osc2 pins. external clock (ec): external clock signal is directly applied to the osc1 pin. the secondary (lp) oscillator is designed for low power and uses a 32.768 khz crystal or ceramic resonator. the lp oscillator uses the sosci and sosco pins. the low-power rc (lprc) inter nal oscillator runs at a nominal frequency of 32.768 khz. it is also used as a reference clock by the watchdog timer (wdt) and fail-safe clock monitor (fscm). the clock signals generated by the frc and primary oscillators can be optionally applied to an on-chip pll to provide a wide range of output frequencies for device operation. pll configuration is described in section 9.1.4 pll configuration . the frc frequency depends on the frc accuracy (see table 30-19 ) and the value of the frc oscillator tuning register (see register 9-4 ). 9.1.2 system clock selection the oscillator source used at a device power-on reset event is selected using configuration bit settings. the oscillator configuration bit settings are located in the configuration registers in the program memory. (refer to section 27.1 configuration bits for further details.) the initial oscillator selection configuration bits, fnosc<2:0> (foscsel<2:0>), and the primary oscillator mode select configuration bits, poscmd<1:0> (fosc<1:0>), select the osc illator source that is used at a power-on reset. the frc primary oscillator is the default (unprogrammed) selection. the configuration bits allow users to choose among 12 different clock modes, shown in ta b l e 9 - 1 . the output of the oscillator (or the output of the pll if a pll mode has been selected) f osc is divided by 2 to generate the device instruction clock (f cy ) and peripheral clock time base (f p ). f cy defines the operating speed of the dev ice, and speeds up to 40 mhz are supported by the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 architecture. instruction execution speed or device operating frequency, f cy , is given by: equation 9-1: device operating frequency 9.1.3 auxiliary oscillator the auxiliary oscillator (aosc) can be used for periph- erals that need to operate at a frequency unrelated to the system clock such as a digital-to-analog converter (dac). the auxiliary oscillator can use one of the following as its clock source: crystal (xt): crystal and ceramic resonators in the range of 3 mhz to 10 mhz. the crystal is connected to the soci and sosco pins. high-speed crystal (hs): crystals in the range of 10 to 40 mhz. the crystal is connected to the sosci and sosco pins. external clock (ec): extern al clock signal up to 64 mhz. the external clock signal is directly applied to sosci pin. f cy f osc 2 ------------- = downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 143 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 9.1.4 pll configuration the primary oscillator and internal frc oscillator can optionally use an on-chip pll to obtain higher speeds of operation. the pll provides significant flexibility in selecting the device operating speed. a block diagram of the pll is shown in figure 9-2 . the output of the primary oscillator or frc, denoted as f in , is divided down by a prescale factor (n1) of 2, 3, ... or 33 before being provided to the plls voltage controlled oscillator (vco). the input to the vco must be selected in the range of 0.8 mhz to 8 mhz. the prescale factor n1 is selected using the pllpre<4:0> bits (clkdiv<4:0>). the pll feedback divisor, selected using the plldiv<8:0> bits (pllfbd<8:0>), provides a factor m, by which the input to the vc o is multiplied. this factor must be selected such that the resulting vco output frequency is in the range of 100 mhz to 200 mhz. the vco output is further divided by a postscale factor n2. this factor is selected using the pllpost<1:0> bits (clkdiv<7:6>). n2 can be either 2, 4 or 8, and must be selected such that the pll output frequency (f osc ) is in the range of 12.5 mhz to 80 mhz, which generates device operating speeds of 6.25-40 mips. for a primary oscillator or frc oscillator, output f in , the pll output f osc is given by: equation 9-2: f osc calculation for example, suppose a 10 mhz crystal is being used with the selected oscillato r mode of xt with pll. if pllpre<4:0> = 0 , then n1 = 2. this yields a vco input of 10/2 = 5 mhz, which is within the acceptable range of 0.8-8 mhz. if plldiv<8:0> = 0x1e, then m = 32. this yields a vco output of 5 x 32 = 160 mhz, which is within the 100-200 mhz ranged needed. if pllpost<1:0> = 0 , then n2 = 2. this provides a fosc of 160/2 = 80 mhz. the resultant device operating speed is 80/2 = 40 mips. equation 9-3: xt with pll mode example figure 9-2: dspic33fj32gp302/304, dspi c33fj64gpx02/x04, and dspic33fj128gpx02/ x04 pll block diagram f osc f in m n 1 n 2 ? -------------------- - ?? ?? ? = f cy f osc 2 ------------- 12 -- - 10000000 32 ? 22 ? ----------------------------------- - ?? ?? 40 mips = == 0.8-8.0 mhz (1) 100-200 mhz (1) divide by 2, 4, 8 divide by 2-513 divide by 2-33 source (crystal, external clock pllpre x vco plldiv pllpost or internal rc) 12.5-80 mhz (1) f osc note 1: this frequency range must be satisfied at all times. n1 m n2 f vco downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 144 ? 2007-2012 microchip technology inc. table 9-1: configuration bit values for clock selection 9.2 oscillator resources many useful resources related to the oscillator are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 9.2.1 key resources section 39. oscillator (part iii) (ds70216) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools oscillator mode oscillator so urce poscmd<1:0> fnosc<2:0> see note fast rc oscillator with divide-by-n (frcdivn) internal xx 111 1, 2 fast rc oscillator with divide-by-16 (frcdiv16) internal xx 110 1 low-power rc oscillator (lprc) internal xx 101 1 secondary (timer1) oscillator (sosc) secondary xx 100 1 primary oscillator (hs) with pll (hspll) primary 10 011 primary oscillator (xt) with pll (xtpll) primary 01 011 primary oscillator (ec) with pll (ecpll) primary 00 011 1 primary oscillator (hs) primary 10 010 primary oscillator (xt) primary 01 010 primary oscillator (ec) primary 00 010 1 fast rc oscillator with pll (frcpll) internal xx 001 1 fast rc oscillator (frc) internal xx 000 1 note 1: osc2 pin function is determined by the osciofnc configuration bit. 2: this is the default oscillator mode for an unprogrammed (erased) device. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 145 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 9.3 oscillator control registers register 9-1: osccon: os cillator control register (1,3) u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y cosc<2:0> nosc<2:0> (2) bit 15 bit 8 r/w-0 r/w-0 r-0 u-0 r/c-0 u-0 r/w-0 r/w-0 clklock iolock lock c f lposcen oswen bit 7 bit 0 legend: y = value set from configuration bits on por c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 cosc<2:0>: current oscillator selection bits (read-only) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcdivn + pll) 000 = fast rc oscillator (frc) bit 11 unimplemented: read as 0 bit 10-8 nosc<2:0>: new oscillator selection bits (2) 111 = fast rc oscillator (frc) with divide-by-n 110 = fast rc oscillator (frc) with divide-by-16 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (sosc) 011 = primary oscillator (xt, hs, ec) with pll 010 = primary oscillator (xt, hs, ec) 001 = fast rc oscillator (frc) with divide-by-n and pll (frcdivn + pll) 000 = fast rc oscillator (frc) bit 7 clklock: clock lock enable bit if clock switching is enabled and fscm is disabled, fcksm<1:0> (fosc< 7:6>) = 0b01 1 = clock switching is disabled, system clock source is locked 0 = clock switching is enabled, system clock s ource can be modified by clock switching bit 6 iolock: peripheral pin select lock bit 1 = peripherial pin select is locked, write to peripheral pin select registers not allowed 0 = peripherial pin select is not locked, write to peripheral pin select registers allowed bit 5 lock: pll lock status bit (read-only) 1 = indicates that pll is in lock, or pll start-up timer is satisfied 0 = indicates that pll is out of lock, start-up timer is in progress or pll is disabled bit 4 unimplemented: read as 0 note 1: writes to this register require an unlock sequence. refer to section 39. oscillator (part iii) (ds70216) in the dspic33f/pic24h family reference manual (available from the microchip website) for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: this register is reset only on a power-on reset (por). downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 146 ? 2007-2012 microchip technology inc. bit 3 cf: clock fail detect bit (read/clear by application) 1 = fscm has detect ed clock failure 0 = fscm has not dete cted clock failure bit 2 unimplemented: read as 0 bit 1 lposcen: secondary (lp) oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = request oscillator switch to se lection specified by nosc<2:0> bits 0 = oscillator switch is complete register 9-1: osccon: os cillator control register (1,3) (continued) note 1: writes to this register require an unlock sequence. refer to section 39. oscillator (part iii) (ds70216) in the dspic33f/pic24h family reference manual (available from the microchip website) for details. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the applic ation must switch to frc mode as a transition clock source between the two pll modes. 3: this register is reset only on a power-on reset (por). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 147 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 9-2: clkdiv: clock divisor register (2) r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 roi doze<2:0> dozen (1) frcdiv<2:0> bit 15 bit 8 r/w-0 r/w-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pllpost<1:0> pllpre<4:0> bit 7 bit 0 legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 roi: recover on interrupt bit 1 = interrupts clears the dozen bit and the proce ssor clock/peripheral clo ck ratio is set to 1:1 0 = interrupts have no effect on the dozen bit bit 14-12 doze<2:0>: processor clock reduction select bits 111 = f cy /128 110 = f cy /64 101 = f cy /32 100 = f cy /16 011 = f cy /8 (default) 010 = f cy /4 001 = f cy /2 000 = f cy /1 bit 11 dozen: doze mode enable bit (1) 1 = doze<2:0> field specifies the ratio between the peripheral clocks and the processor clocks 0 = processor clock/peripheral clock ratio forced to 1:1 bit 10-8 frcdiv<2:0>: internal fast rc osci llator postscaler bits 111 = frc divide by 256 110 = frc divide by 64 101 = frc divide by 32 100 = frc divide by 16 011 = frc divide by 8 010 = frc divide by 4 001 = frc divide by 2 000 = frc divide by 1 (default) bit 7-6 pllpost<1:0>: pll vco output divider select bits (also denoted as n2, pll postscaler) 11 = output/8 10 = reserved 01 = output/4 (default) 00 = output/2 bit 5 unimplemented: read as 0 bit 4-0 pllpre<4:0>: pll phase detector input divider bits (also denoted as n1, pll prescaler) 11111 = input/33 00000 = input/2 (default) 00001 = input/3 note 1: this bit is cleared when the roi bit is set and an interrupt occurs. 2: this register is reset only on a power-on reset (por). downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 148 ? 2007-2012 microchip technology inc. register 9-3: pllfbd: pll feedback divisor register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 p l l d i v < 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 plldiv<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-9 unimplemented: read as 0 bit 8-0 plldiv<8:0>: pll feedback divisor bits (also denoted as m, pll multiplier) 111111111 = 513 000110000 = 50 (default) 000000010 = 4 000000001 = 3 000000000 = 2 note 1: this register is reset only on a power-on reset (por). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 149 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 9-4: osctun: frc os cillator tuning register (2) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tun<5:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-6 unimplemented: read as 0 bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 111111 = center frequency -0.375% (7.345 mhz) 100001 = center frequency -11.625% (6.52 mhz) 100000 = center frequency -12% (6.49 mhz) 011111 = center frequency +11.625% (8.23 mhz) 011110 = center frequency +11.25% (8.20 mhz) 000001 = center frequency +0.375% (7.40 mhz) 000000 = center frequency (7.37 mhz nominal) note 1: osctun functionality has been provided to help cu stomers compensate for temperature effects on the frc frequency over a wide range of temperatures. the t uning step size is an approximation and is neither characterized nor tested. 2: this register is reset only on a power-on reset (por). downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 150 ? 2007-2012 microchip technology inc. register 9-5: aclkcon: auxiliary control register (1) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 selaclk aoscmd<1:0> apstsclr<2:0> bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 asrcsel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 selaclk: select auxiliary clock source for auxiliary clock divider 1 = auxiliary oscillators provides the source clock for au xiliary clock divider 0 = pll output (fosc) provides the source clock for the auxiliary clock divider bit 12-11 aoscmd<1:0>: auxiliary oscillator mode 11 = ec external clock mode select 10 = xt oscillator mode select 01 = hs oscillator mode select 00 = auxiliary oscillator disabled bit 10-8 apstsclr<2:0>: auxiliary clock output divider 111 = divided by 1 110 = divided by 2 101 = divided by 4 100 = divided by 8 011 = divided by 16 010 = divided by 32 001 = divided by 64 000 = divided by 256 (default) bit 7 asrcsel: select reference clock source for auxiliary clock 1 = primary oscillator is the clock source 0 = auxiliary oscillator is the clock source bit 6-0 unimplemented: read as 0 note 1: this register is reset only on a power-on reset (por). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 151 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 9.4 clock switching operation applications are free to s witch among any of the four clock sources (primary, lp, frc and lprc) under software control at any time . to limit the possible side effects of this flexibilit y, dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices have a safeguard lock built into the switch process. 9.4.1 enabling clock switching to enable clock switching, the fcksm1 configuration bit in the configuration register must be programmed to 0 . (refer to section 27.1 configuration bits for further details.) if the fcksm1 configuration bit is unprogrammed ( 1 ), the clock switching function and fail-safe clock monitor function are disabled. this is the default setting. the nosc control bits (osccon<10:8>) do not control the clock selecti on when clock switching is disabled. however, the cosc bits (osccon<14:12>) reflect the clock source selected by the fnosc configuration bits. the oswen control bit (osccon<0>) has no effect when clock switching is disabled. it is held at 0 at all times. 9.4.2 oscillator switching sequence performing a clock switch requires this basic sequence: 1. if desired, read the cosc bits (osccon<14:12>) to determine the current oscillator source. 2. perform the unlock sequence to allow a write to the osccon register high byte. 3. write the appropriate value to the nosc control bits (osccon<10:8>) for the new oscillator source. 4. perform the unlock sequence to allow a write to the osccon register low byte. 5. set the oswen bit (osccon<0>) to initiate the oscillator switch. once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. the clock switching hardware compares the cosc status bits with the new value of the nosc control bits. if they are the same, the clock switch is a redundant operation. in this case, the oswen bit is cleared automatically and the clock switch is aborted. 2. if a valid clock switch has been initiated, the status bits, lock (osccon<5>) and the cf (osccon<3>) are cleared. 3. the new oscillator is turned on by the hardware if it is not currently running. if a crystal oscillator must be turned on, the hardware waits until the oscillator start-up timer (ost) expires. if the new source is using the pll, the hardware waits until a pll lock is detected (lock = 1 ). 4. the hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. 5. the hardware clears the oswen bit to indicate a successful clock transition. in addition, the nosc bit values are transferred to the cosc status bits. 6. the old clock source is turned off at this time, with the exception of lprc (if wdt or fscm are enabled) or lp (if lposcen remains set). 9.5 fail-safe clock monitor (fscm) the fail-safe clock monitor (fscm) allows the device to continue to operate even in the event of an oscillator failure. the fscm function is enabled by programming. if the fscm function is enabled, the lprc internal oscillator runs at all times (except during sleep mode) and is not subject to control by the watchdog timer. in the event of an oscillator failure, the fscm generates a clock failure tr ap event and switches the system clock over to the frc oscillator. then the application program can either attempt to restart the oscillator or execute a controlled shutdown. the trap can be treated as a warm reset by simply loading the reset address into the os cillator fail trap vector. if the pll multiplier is used to scale the system clock, the internal frc is also multiplied by the same factor on clock failure. es sentially, the device switches to frc with pll on a clock failure. note: primary oscillator mode has three different submodes (xt, hs and ec), which are determined by the poscmd<1:0> config- uration bits. while an application can switch to and from primary oscillator mode in software, it cannot switch among the different primary submodes without reprogramming the device. note 1: the processor continues to execute code throughout the clock switching sequence. timing-sensitive code should not be executed during this time. 2: direct clock switches between any primary oscillator mode with pll and frcpll mode are not permitted. this applies to clock switches in either direction. in these instances, the application must switch to frc mode as a transition clock source between the two pll modes. 3: refer to section 39. oscillator (part iii) (ds70216) in the dspic33f/pic24h family reference manual for details. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 152 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 153 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 10.0 power-saving features the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 devices provide the ability to manage power consumption by selectively managing clocking to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices can manage power consumption in four ways: clock frequency instruction-based sleep and idle modes software-controlled doze mode selective peripheral control in software combinations of these methods can be used to selec- tively tailor an applications power consumption while still maintaining critical application features, such as timing-sensitive communications. 10.1 clock frequency and clock switching dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices allow a wide range of clock frequencies to be selected under application control. if the syst em clock configuration is not locked, users can choose low-power or high- precision oscillators by si mply changing the nosc bits (osccon<10:8>). the process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in section 9.0 oscillator configuration . 10.2 instruction-based power-saving modes dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices have two special power-saving modes that are entered through the execution of a special pwrsav instruction. sleep mode stops clock operation and halts all code execution. idle mode halts the cpu and code execution, but allows peri pheral modules to continue operation. the assembler syntax of the pwrsav instruction is shown in example 10-1 . sleep and idle modes can be exited as a result of an enabled interrupt, wdt time-out or a device reset. when the device exits these modes, it is said to wake up. 10.2.1 sleep mode the following occur in sleep mode: the system clock source is shut down. if an on-chip oscillator is used, it is turned off. the device current consumption is reduced to a minimum, provided that no i/o pin is sourcing current. the fail-safe clock monitor does not operate, since the system clock source is disabled. the lprc clock continues to run in sleep mode if the wdt is enabled. the wdt, if enabled, is automatically cleared prior to entering sleep mode. some device features or peripherals can continue to operate. this includes items such as the input change notification on the i/o ports, or peripherals that use an external clock input. any peripheral that r equires the system clock source for its operation is disabled. the device wakes up from sleep mode on any of these events: any interrupt source that is individually enabled any form of device reset a wdt time-out on wake-up from sleep mode, the processor restarts with the same clock source th at was active when sleep mode was entered. example 10-1: pwrsav instruction syntax note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 9. watchdog timer and power-saving modes (ds70196) of the dspic33f/pic24h family refer- ence manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: sleep_mode and idle_mode are con- stants defined in the assembler include file for the selected device. pwrsav #sleep_mode ; put the device into sleep mode pwrsav #idle_mode ; put the device into idle mode downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 154 ? 2007-2012 microchip technology inc. 10.2.2 idle mode the following occur in idle mode: the cpu stops executing instructions. the wdt is automatically cleared. the system clock sour ce remains active. by default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see section 10.4 peripheral module disable ). if the wdt or fscm is enabled, the lprc also remains active. the device wakes from idle mode on any of these events: any interrupt that is individually enabled any form of device reset a wdt time-out on wake-up from idle mode, the clock is reapplied to the cpu and instruction execution will begin (2-4 clock cycles later), starting with the instruction following the pwrsav instruction, or the first instruction in the isr. 10.2.3 interrupts coincident with power save instructions any interrupt that coincides with the execution of a pwrsav instruction is held off until entry into sleep or idle mode has completed. the device then wakes up from sleep or idle mode. 10.3 doze mode the preferred strategies for reducing power consumption are changing clock speed and invoking one of the power-saving modes. in some circumstances, this cannot be practical. for example, it may be necessary for an application to maintain uninterrupted synchronous co mmunication, even while it is doing nothing else. reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely. doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. in this mode, the system clock continues to operate from th e same source and at the same speed. peripheral modules continue to be clocked at the same speed, while the cpu clock speed is reduced. synchronization between the two clock domains is maintained, allowing the peripherals to access the sfrs while the cpu executes code at a slower rate. doze mode is enabled by setting the dozen bit (clkdiv<11>). the ratio between peripheral and core clock speed is determined by the doze<2:0> bits (clkdiv<14:12>). there are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default setting. programs can use doze mode to selectively reduce power consumption in event-driven applications. this allows clock-sensitive func tions, such as synchronous communications, to continue without interruption while the cpu idles, waiting for something to invoke an interrupt routine. an automatic return to full-speed cpu operation on interrupts can be enabled by setting the roi bit (clkdiv<15>). by default, interrupt events have no effect on doze mode operation. for example, suppose the device is operating at 20 mips and the ecan module has been configured for 500 kbps based on this device operating speed. if the device is placed in doze mode with a clock frequency ratio of 1:4, the ecan module continues to communicate at the required bit rate of 500 kbps, but the cpu now starts execut ing instructions at a frequency of 5 mips. 10.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabl ed using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those register s do not have effect and read values are invalid. a peripheral module is enabled only if both the associated bit in the pmd register is cleared and the peripheral is supported by the specific dspic ? dsc variant. if the peripheral is present in the device, it is enabled in the pmd register by default. note: if a pmd bit is set, the corresponding mod- ule is disabled after a delay of one instruc- tion cycle. similarly, if a pmd bit is cleared, the corresponding module is enabled after a delay of one inst ruction cycle (assuming the module control registers are already configured to enable module operation). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 155 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 10.5 power-saving resources many useful resources related to power-saving are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 10.5.1 key resources section 9. watchdog timer and power-saving modes (ds70196) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 156 ? 2007-2012 microchip technology inc. 10.6 power-saving control registers register 10-1: pmd1: peripheral module disable control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 t5md t4md t3md t2md t1md dcimd bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 i2c1md u2md u1md spi2md spi1md c 1 m da d 1 m d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 t5md: timer5 module disable bit 1 = timer5 module is disabled 0 = timer5 module is enabled bit 14 t4md: timer4 module disable bit 1 = timer4 module is disabled 0 = timer4 module is enabled bit 13 t3md: timer3 module disable bit 1 = timer3 module is disabled 0 = timer3 module is enabled bit 12 t2md: timer2 module disable bit 1 = timer2 module is disabled 0 = timer2 module is enabled bit 11 t1md: timer1 module disable bit 1 = timer1 module is disabled 0 = timer1 module is enabled bit 10-9 unimplemented: read as 0 bit 8 dcimd: dci module disable bit 1 = dci module is disabled 0 = dci module is enabled bit 7 i2c1md: i 2 c1 module disable bit 1 = i 2 c1 module is disabled 0 = i 2 c1 module is enabled bit 6 u2md: uart2 module disable bit 1 = uart2 module is disabled 0 = uart2 module is enabled bit 5 u1md: uart1 module disable bit 1 = uart1 module is disabled 0 = uart1 module is enabled bit 4 spi2md: spi2 module disable bit 1 = spi2 module is disabled 0 = spi2 module is enabled bit 3 spi1md: spi1 module disable bit 1 = spi1 module is disabled 0 = spi1 module is enabled bit 2 unimplemented: read as 0 bit 1 c1md: ecan1 module disable bit 1 = ecan1 module is disabled 0 = ecan1 module is enabled bit 0 ad1md: adc1 module disable bit 1 = adc1 module is disabled 0 = adc1 module is enabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 157 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 10-2: pmd2: peripheral module disable control register 2 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ic8md ic7md i c 2 m di c 1 m d bit 15 bit 8 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 oc4md oc3md oc2md oc1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ic8md: input capture 8 module disable bit 1 = input capture 8 module is disabled 0 = input capture 8 module is enabled bit 14 ic7md: input capture 2 module disable bit 1 = input capture 7 module is disabled 0 = input capture 7 module is enabled bit 13-10 unimplemented: read as 0 bit 9 ic2md: input capture 2 module disable bit 1 = input capture 2 module is disabled 0 = input capture 2 module is enabled bit 8 ic1md: input capture 1 module disable bit 1 = input capture 1 module is disabled 0 = input capture 1 module is enabled bit 7-4 unimplemented: read as 0 bit 3 oc4md: output compare 4 module disable bit 1 = output compare 4 module is disabled 0 = output compare 4 module is enabled bit 2 oc3md: output compare 3 module disable bit 1 = output compare 3 module is disabled 0 = output compare 3 module is enabled bit 1 oc2md: output compare 2 module disable bit 1 = output compare 2 module is disabled 0 = output compare 2 module is enabled bit 0 oc1md: output compare 1 module disable bit 1 = output compare 1 module is disabled 0 = output compare 1 module is enabled downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 158 ? 2007-2012 microchip technology inc. register 10-3: pmd3: peripheral module disable control register 3 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 cmpmd rtccmd pmpmd bit 15 bit 8 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 crcmd dac1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10 cmpmd: comparator module disable bit 1 = comparator module is disabled 0 = comparator module is enabled bit 9 rtccmd: rtcc module disable bit 1 = rtcc module is disabled 0 = rtcc module is enabled bit 8 pmpmd: pmp module disable bit 1 = pmp module is disabled 0 = pmp module is enabled bit 7 crcmd: crc module disable bit 1 = crc module is disabled 0 = crc module is enabled bit 6 dac1md: dac1 module disable bit 1 = dac1 module is disabled 0 = dac1 module is enabled bit 5-0 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 159 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 11.0 i/o ports all of the device pins (except v dd , v ss , mclr and osc1/clki) are shared among the peripherals and the parallel i/o ports. all i/o input ports feature schmitt trigger inputs for improved noise immunity. 11.1 parallel i/o (pio) ports generally a parallel i/o port that shares a pin with a peripheral is subservient to the peripheral. the peripherals output buffer data and control signals are provided to a pair of multiplexers. the multiplexers select whether the peripher al or the associated port has ownership of the output data and control signals of the i/o pin. the logic also prevents loop through, in which a ports digital output can drive the input of a peripheral that shares the same pin. figure 11-1 shows how ports are shared with other peripherals and the associated i/o pin to which they are connected. when a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. the i/o pin can be read, but the output driver for the parallel port bit is disabled. if a peripheral is enabled, but the peripheral is not actively driving a pin, that pin can be driven by a port. all port pins have three registers directly associated with their operation as digital i/o. the data direction register (trisx) determines whether the pin is an input or an output. if the data direction bit is a 1 , then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write t he latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. any bit and its associated data and control registers that are not valid for a particular device is disabled. this means the corresponding latx and trisx registers and the port pin are read as zeros. when a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless regarded as a dedicated port because there is no other compet ing source of outputs. figure 11-1: block diagram of a typical shared port structure note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 30. i/o ports with peripheral pin select (ds70190) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. q d ck wr lat + tris latch i/o pin wr port data bus q d ck data latch read port read tris 10 1 0 wr tris peripheral output data output enable peripheral input data i/o peripheral module peripheral output enable pio module output multiplexers output data input data peripheral module enable read lat downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 160 ? 2007-2012 microchip technology inc. 11.2 open-drain configuration in addition to the port, lat and tris registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open -drain contro l register, odcx, associated with each port. setting any of the bits configures the corresponding pin to act as an open-drain output. the open-drain feature a llows the generation of outputs higher than v dd (e.g., 5v) on any desired 5v tolerant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. refer to pin diagrams for the available pins and their functionality. 11.3 configuring analog port pins the ad1pcfgl and tris registers control the opera- tion of the analog-to-digital (adc) port pins. the port pins that are to function as analog inputs must have their corresponding tris bit set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) is converted. the ad1pcfgl register has a default value of 0x0000; therefore, all pins that s hare anx functions are analog (not digital) by default. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 11.4 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop , as shown in example 11-1 . 11.5 input change notification the input change notification function of the i/o ports allows the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. this feature can detect input change-of- states even in sleep mode, when the clocks are disabled. depending on the device pin count, up to 21 external signals (cnx pin) can be selected (enabled) for generating an interrupt request on a change-of- state. four control registers are associated with the cn mod- ule. the cnen1 and cnen2 registers contain the interrupt enable control bits for each of the cn input pins. setting any of these bits enables a cn interrupt for the corresponding pins. each cn pin also has a weak pull-up connected to it. the pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when push-button or keypad de vices are connected. the pull-ups are enabled separately using the cnpu1 and cnpu2 registers, which contain the control bits for each of the cn pins. sett ing any of the control bits enables the weak pull-ups for the corresponding pins. example 11-1: port write/read example note: pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. mov 0xff00, w0 ; configure portb<15:8> as inputs mov w0, trisbb ; and portb<7:0> as outputs nop ; delay 1 cycle btss portb, #13 ; next instruction downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 161 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 11.6 peripheral pin select peripheral pin select configuration enables peripheral set selection and placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature operates over a fixed subset of digital i/o pins. programmers can independently map the input and/or output of most digital peripherals to any one of these i/o pins. peripheral pin select is performed in software, and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping, once it has been established. 11.6.1 available pins the peripheral pin select feature is used with a range of up to 26 pins. the number of available pins depends on the particular device and its pin count. pins that support the peripheral pin se lect feature include the designation rpn in their full pin designation, where rp designates a remappable peripheral and n is the remappable pin number. 11.6.2 controlling peripheral pin select peripheral pin select features are controlled through two sets of special functi on registers: one to map peripheral inputs, and one to map outputs. because they are separately controlled, a particular peripherals input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. 11.6.2.1 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. a control register associated with a peripheral dictates the pin it is mapped to. the rpinrx registers are used to configure peripheral input mapping (see register 11-1 through register 11-16 ). each register contains sets of 5-bit fields, with each set associated with one of the remappable peripherals. programming a given peripherals bit field with an appropriate 5-bit value maps the rpn pin with that value to that peripheral. for any given device, the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device. figure 11-2 illustrates remappable pin selection for u1rx input. figure 11-2: remappable mux input for u1rx note: for input mapping only, the peripheral pin select (pps) functionality does not have priority over the trisx settings. therefore, when configuring the rpx pin for input, the corresponding bit in the trisx register must also be configured for input (i.e., set to 1 ). rp0 rp1 rp2 rp 25 0 25 12 u1rx input u1rxr<4:0> to peripheral downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 162 ? 2007-2012 microchip technology inc. table 11-1: selectable input sources (maps input to function) (1) input name function name register configuration bits external interrupt 1 int1 rpinr0 int1r<4:0> external interrupt 2 int2 rpinr1 int2r<4:0> timer2 external clock t2ck rpinr3 t2ckr<4:0> timer3 external clock t3ck rpinr3 t3ckr<4:0> timer4 external clock t4ck rpinr4 t4ckr<4:0> timer5 external clock t5ck rpinr4 t5ckr<4:0> input capture 1 ic1 rpinr7 ic1r<4:0> input capture 2 ic2 rpinr7 ic2r<4:0> input capture 7 ic7 rpinr10 ic7r<4:0> input capture 8 ic8 rpinr10 ic8r<4:0> output compare fault a ocfa rpinr11 ocfar<4:0> uart1 receive u1rx rpinr18 u1rxr<4:0> uart1 clear to send u1cts rpinr18 u1ctsr<4:0> uart2 receive u2rx rpinr19 u2rxr<4:0> uart2 clear to send u2cts rpinr19 u2ctsr<4:0> spi1 data input sdi1 rpinr20 sdi1r<4:0> spi1 clock input sck1 rpinr20 sck1r<4:0> spi1 slave select input ss1 rpinr21 ss1r<4:0> spi2 data input sdi2 rpinr22 sdi2r<4:0> spi2 clock input sck2 rpinr22 sck2r<4:0> spi2 slave select input ss2 rpinr23 ss2r<4:0> dci serial data input csdi rpinr24 csdir<4:0> dci serial clock input csck rpinr24 csckr<4:0> dci frame sync input cofs rpinr25 cofsr<4:0> ecan1 receive cirx rpinr26 cirxr<4:0> note 1: unless otherwise noted, all inputs use schmitt input buffers. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 163 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 11.6.2.2 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control register associated with a particular pin dictates the peripheral output to be mapped. the rporx registers are used to control output mapping. like the rpinrx registers, each register contains sets of 5-bit fields, with each set associated with one rpn pin (see register 11-17 through register 11-29 ). the value of the bit field corresponds to one of the peripherals, and that perip herals output is mapped to the pin (see ta b l e 11 - 2 and figure 11-3 ). the list of peripherals for output mapping also includes a null value of 00000 because of the mapping technique. this permits any given pin to remain unconnected from the outpu t of any of the pin selectable peripherals. figure 11-3: multiplexing of remappable output for rpn table 11-2: output selection for remappable pin (rpn) 0 21 3 rpnr<4:0> default u1tx output enable u1rts output enable 4 oc4 output 0 21 3 default u1tx output u1rts output 4 oc4 output output enable output data rpn function rpnr<4:0> output name null 00000 rpn tied to default port pin c1out 00001 rpn tied to comparator1 output c2out 00010 rpn tied to comparator2 output u1tx 00011 rpn tied to uart1 transmit u1rts 00100 rpn tied to uart1 ready to send u2tx 00101 rpn tied to uart2 transmit u2rts 00110 rpn tied to uart2 ready to send sdo1 00111 rpn tied to spi1 data output sck1 01000 rpn tied to spi1 clock output ss1 01001 rpn tied to spi1 slave select output sdo2 01010 rpn tied to spi2 data output sck2 01011 rpn tied to spi2 clock output ss2 01100 rpn tied to spi2 slave select output csdo 01101 rpn tied to dci serial data output csck 01110 rpn tied to dci serial clock output cofs 01111 rpn tied to dci frame sync output c1tx 10000 rpn tied to ecan1 transmit oc1 10010 rpn tied to output compare 1 oc2 10011 rpn tied to output compare 2 oc3 10100 rpn tied to output compare 3 oc4 10101 rpn tied to output compare 4 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 164 ? 2007-2012 microchip technology inc. 11.6.3 controlling configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. dspic33f devices include three features to prevent alterations to the peripheral map: control register lock sequence continuous state monitoring configuration bit pin select lock 11.6.3.1 control register lock under normal operation, writ es to the rpinrx and rporx registers are not allowed. attempted writes appear to execute normally, but the contents of the reg- isters remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the iolock bit (osccon<6>). setting iolock prevents writes to the control registers; clearing iolock allows writes. to set or clear iolock, a specific command sequence must be executed: 1. write 0x46 to osccon<7:0>. 2. write 0x57 to osccon<7:0>. 3. clear (or set) iolock as a single operation. unlike the similar sequence with the oscillators lock bit, iolock remains in one state until changed. this allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 11.6.3.2 continuous state monitoring in addition to being protect ed from direct writes, the contents of the rpinrx and rporx registers are constantly monitored in hardware by shadow registers. if an unexpected change in any of the registers occurs (such as cell disturbances caused by esd or other external events), a configuration mismatch reset is triggered. 11.6.3.3 configuration bit pin select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpinrx and rporx regi sters. the iol1way con- figuration bit (fosc<5>) blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one wr ite session. programming iol1way allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. note: mplab ? c30 provides built-in c language functions for unlocking the osccon register: __builtin_write_oscconl(value) __builtin_write_oscconh(value) see mplab help for more information. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 165 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 11.7 i/o helpful tips 1. in some cases, certain pins as defined in table 30-9: dc characteristics: i/o pin input speci- fications under injection current, have internal protection diodes to v dd and v ss . the term injection current is al so referred to as clamp current. on designated pins, with sufficient exter- nal current limiting precautions by the user, i/o pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with nominal v dd with respect to the v ss and v dd supplies. note that when the user application for- ward biases either of the high or low side internal input clamp diodes, that the resulting current being injected into the device that is clamped internally by the v dd and v ss power rails, may affect the adc accuracy by four to six counts. 2. i/o pins that are shared with any analog input pin, (i.e., anx), are always analog pins by default after any reset. consequently, any pin(s) configured as an analog input pin, automatically disables the dig- ital input pin buffer. as such, any attempt to read a digital input pin will always return a 0 regardless of the digital logic level on the pin if the analog pin is configured. to use a pin as a digital i/o pin on a shared anx pin, the user application needs to con- figure the analog pin configuration registers in the adc module, (i.e., adxpcfgl, ad1pcfgh), by setting the appropriate bit that corresponds to that i/o port pin to a 1 . on devices with more than one adc, both analog pin conf igurations for both adc modules must be configured as a digital i/o pin for that pin to function as a digital i/o pin. 3. most i/o pins have multiple functions. referring to the device pin diagrams in the data sheet, the pri- orities of the functions allocated to any pins are indicated by reading the pin name from left-to- right. the left most function name takes prece- dence over any function to its right in the naming convention. for exampl e: an16/t2ck/t7ck/rc1. this indicates that an16 is the highest priority in this example and will super sede all other functions to its right in the list. those other functions to its right, even if enabled, w ould not work as long as any other function to its left was enabled. this rule applies to all of the functions listed for a given pin. 4. each cn pin has a configurable internal weak pull-up resistor. the pull-ups act as a current source connected to the pin, and eliminates the need for external resistors in certain applica- tions. the internal pull-up is to ~(v dd -0.8) not v dd . this is still above the minimum v ih of cmos and ttl devices. 5. when driving leds directly, the i/o pin can source or sink more current than what is specified in the v oh /i oh and v ol /i ol dc characteristic specifica- tion. the respective i oh and i ol current rating only applies to maintaining the corresponding output at or above the v oh and at or below the v ol levels. however, for leds unlike digital inputs of an exter- nally connected device, they are not governed by the same minimum v ih /v il levels. an i/o pin out- put can safely sink or source any current less than that listed in the absolute maximum rating section of the data sheet. for example: v oh = 2.4v @ i oh = -8 ma and v dd = 3.3v the maximum output current sourced by any 8 ma i/o pin = 12 ma. led source current < 12 ma is technically permitted. refer to the v oh /i oh graphs in section 30.0 electrical characteristics for additional information. 11.8 i/o resources many useful resources related to i/o are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 11.8.1 key resources section 10. i/o ports (ds70193) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: although it is not possible to use a digital input pin when its analog function is enabled, it is possible to use the digital i/o output function, tris x = 0x0, while the analog function is also enabled. however, this is not recommended, particularly if the analog input is connected to an external analog voltage source, which would cre- ate signal contention between the analog signal and the output pin driver. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 166 ? 2007-2012 microchip technology inc. 11.9 peripheral pin select registers the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 family of devices implement 33 registers for remappable peripheral configuration: 16 input remappable peripheral registers: - rpinr0-rpinr1, rpinr3-rpinr4, rpinr7, rpinr10-rpinr11 and prinr18-rpinr26 13 output remappable peripheral registers: - rpor0-rpor12 note: input and output register values can only be changed if the iolock bit (osccon<6>) is set to 0 . see section 11.6.3.1 control register lock for a specific command sequence. register 11-1: rpinr0: peripheral pin select input register 0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 i n t 1 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 int1r<4:0>: assign external interrupt 1 (intr1) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-0 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 167 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-2: rpinr1: peripheral pin select input register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 i n t 2 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 int2r<4:0>: assign external interrupt 2 (intr2) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 168 ? 2007-2012 microchip technology inc. register 11-3: rpinr3: peripheral pin select input register 3 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t 3 c k r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t 2 c k r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 t3ckr<4:0>: assign timer3 external clock (t3c k) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 t2ckr<4:0>: assign timer2 external clock (t2c k) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 169 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-4: rpinr4: peripheral pin select input register 4 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t 5 c k r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 t 4 c k r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 t5ckr<4:0>: assign timer5 external clock (t5c k) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 t4ckr<4:0>: assign timer4 external clock (t4c k) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 170 ? 2007-2012 microchip technology inc. register 11-5: rpinr7: peripheral pin select input register 7 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic2r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 ic2r<4:0>: assign input capture 2 (ic2) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 ic1r<4:0>: assign input capture 1 (ic1) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25. 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 171 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-6: rpinr10: peripheral pin select input register 10 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic8r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ic7r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 ic8r<4:0>: assign input capture 8 (ic8) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 ic7r<4:0>: assign input capture 7 (ic7) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 172 ? 2007-2012 microchip technology inc. register 11-7: rpinr11: peripheral pin select input register 11 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 o c f a r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 ocfar<4:0>: assign output compare a (ocfa) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 173 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-8: rpinr18: peripheral pin select input register 18 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u1ctsr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u 1 r x r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 u1ctsr<4:0>: assign uart1 clear to send (u1cts ) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 u1rxr<4:0>: assign uart1 receive (u1rx) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 174 ? 2007-2012 microchip technology inc. register 11-9: rpinr19: peripheral pin select input register 19 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u2ctsr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u 2 r x r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 u2ctsr<4:0>: assign uart2 clear to send (u2cts ) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 u2rxr<4:0>: assign uart2 receive (u2rx) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 175 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-10: rpinr20: periphe ral pin select input register 20 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 s c k 1 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 s d i 1 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 sck1r<4:0>: assign spi1 clock input (sck1) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 sdi1r<4:0>: assign spi1 data input (sdi1) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 176 ? 2007-2012 microchip technology inc. register 11-11: rpinr21: peripheral pin select input register 21 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ss1r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 ss1r<4:0>: assign spi1 slave select input (ss1 ) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 177 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-12: rpinr22: periphe ral pin select input register 22 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 s c k 2 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 s d i 2 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 sck2r<4:0>: assign spi2 clock input (sck2) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 7-5 unimplemented: read as 0 bit 4-0 sdi2r<4:0>: assign spi2 data input (sdi2) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 178 ? 2007-2012 microchip technology inc. register 11-13: rpinr23: peripheral pin select input register 23 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ss2r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 ss2r<4:0>: assign spi2 slave select input (ss2 ) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 179 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-14: rpinr24: periphe ral pin select input register 24 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 csckr<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c s d i r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 csckr<4:0>: assign dci serial clock input (csck) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 bit 4-0 csdir<4:0>: assign dci serial data input (csdi) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 180 ? 2007-2012 microchip technology inc. register 11-15: rpinr25: peripheral pin select input register 25 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 cofsr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 cofsr<4:0>: assign dci frame sync input (cofs) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 register 11-16: rpinr26: peripheral pin select input register 26 (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c 1 r x r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 c1rxr<4:0>: assign ecan1receive (c1rx) to the corresponding rpn pin 11111 = input tied to v ss 11001 = input tied to rp25 00001 = input tied to rp1 00000 = input tied to rp0 note 1: this register is disabled on devices without an ecan? module. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 181 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-17: rpor0: peripheral pin select output register 0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 1 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 0 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp1r<4:0>: peripheral output function is assigned to rp1 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp0r<4:0>: peripheral output function is assigned to rp0 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) register 11-18: rpor1: peripheral pin select output register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 3 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 2 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp3r<4:0>: peripheral output function is assigned to rp3 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp2r<4:0>: peripheral output function is assigned to rp2 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 182 ? 2007-2012 microchip technology inc. register 11-19: rpor2: peripheral pin select output register 2 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp5r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp4r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp5r<4:0>: peripheral output function is assigned to rp5 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp4r<4:0>: peripheral output function is assigned to rp4 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) register 11-20: rpor3: peripheral pin select output register 3 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp7r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp6r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp7r<4:0>: peripheral output function is assigned to rp7 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp6r<4:0>: peripheral output function is assigned to rp6 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 183 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-21: rpor4: peripheral pin select output register 4 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 9 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 8 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp9r<4:0>: peripheral output function is assigned to rp9 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp8r<4:0>: peripheral output function is assigned to rp8 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) register 11-22: rpor5: peripheral pin select output register 5 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r p 1 1 r < 4 : 0 > bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp10r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp11r<4:0>: peripheral output function is assigned to rp11 output pin bits (see table 11-2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp10r<4:0>: peripheral output function is a ssigned to rp10 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 184 ? 2007-2012 microchip technology inc. register 11-23: rpor6: peripheral pin select output register 6 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp13r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp12r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp13r<4:0>: peripheral output function is assi gned to rp13 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp12r<4:0>: peripheral output function is a ssigned to rp12 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) register 11-24: rpor7: peripheral pin select output register 7 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp15r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp14r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp15r<4:0>: peripheral output function is assi gned to rp15 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp14r<4:0>: peripheral output function is a ssigned to rp14 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 185 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-25: rpor8: peripheral pin select output register 8 (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp17r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp16r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp17r<4:0>: peripheral output function is assi gned to rp17 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp16r<4:0>: peripheral output function is a ssigned to rp16 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) note 1: this register is implemented in 44-pin devices only. register 11-26: rpor9: peripheral pin select output register 9 (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp19r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp18r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp19r<4:0>: peripheral output function is assi gned to rp19 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp18r<4:0>: peripheral output function is a ssigned to rp18 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) note 1: this register is implemented in 44-pin devices only. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 186 ? 2007-2012 microchip technology inc. register 11-27: rpor10: periphera l pin select output register 10 (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp21r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp20r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp21r<4:0>: peripheral output function is assi gned to rp21 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp20r<4:0>: peripheral output function is a ssigned to rp20 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) note 1: this register is implemented in 44-pin devices only. register 11-28: rpor11: periphera l pin select output register 11 (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp23r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp22r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp23r<4:0>: peripheral output function is assi gned to rp23 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp22r<4:0>: peripheral output function is a ssigned to rp22 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) note 1: this register is implemented in 44-pin devices only. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 187 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 11-29: rpor12: peripheral pin select output register 12 (1) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp25r<4:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rp24r<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 rp25r<4:0>: peripheral output function is assi gned to rp25 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) bit 7-5 unimplemented: read as 0 bit 4-0 rp24r<4:0>: peripheral output function is a ssigned to rp24 output pin bits (see ta b l e 11 - 2 for peripheral function numbers) note 1: this register is implemented in 44-pin devices only. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 188 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 189 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 12.0 timer1 the timer1 module is a 16- bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter. the timer1 module has the following unique features over other timers: can be operated from the low power 32 khz crystal oscillator available on the device can be operated in asynchronous counter mode from an external clock source. the external clock input (t1ck) can optionally be synchronized to the internal device clock and the clock synchronization is performed after the prescaler. the unique features of timer1 allow it to be used for real-time clock (rtc) applications. a block diagram of timer1 is shown in figure 12-1 . the timer1 module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode asynchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous and asynchronous counter modes, the input clock is derived from the external clock input at the t1ck pin. the timer modes are determined by the following bits: timer clock source cont rol bit (tcs): t1con<1> timer synchronization control bit (tsync): t1con<2> timer gate control bit (tgate): t1con<6> timer control bit setting for different operating modes are given in the table 12-1 . table 12-1: timer mode settings figure 12-1: 16-bit timer1 module block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 11. timers (ds70205) of the dspic33f/pic24h family refer- ence manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. mode tcs tgate tsync timer 00x gated timer 01x synchronous counter 1x1 asynchronous counter 1x0 tgate tcs 00 10 x1 tmr1 comparator pr1 tgate set t1if flag 0 1 tsync 1 0 sync equal reset sosci sosco/ t1ck prescaler (/n) tckps<1:0> gate sync f cy falling edge detect prescaler (/n) tckps<1:0> lposcen (1) note 1: refer to section 9.0 oscillator configuration for information on enabling the secondary oscillator. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 190 ? 2007-2012 microchip technology inc. 12.1 timer resources many useful resources related to timers are provided on the main product page of the microchip web site for the devices listed in this dat a sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 12.1.1 key resources section 11. timers (ds70205) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 191 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 12.2 timer1 control register register 12-1: t1con: timer1 control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate tckps<1:0> tsync tcs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timer1 on bit 1 = starts 16-bit timer1 0 = stops 16-bit timer1 bit 14 unimplemented: read as 0 bit 13 tsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timer1 gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer1 input clock prescale select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 unimplemented: read as 0 bit 2 tsync: timer1 external clock input synchronization select bit when tcs = 1 : 1 = synchronize external clock input 0 = do not synchronize external clock input when tcs = 0 : this bit is ignored. bit 1 tcs: timer1 clock source select bit 1 = external clock from pin t1ck (on the rising edge) 0 = internal clock (f cy ) bit 0 unimplemented: read as 0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 192 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 193 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 13.0 timer2/3 and timer4/5 feature timer2 and timer4 are type b timers with the following specific features: a type b timer can be concatenated with a type c timer to form a 32-bit timer the external clock input (txck) is always synchronized to the inter nal device clock and the clock synchronization is performed after the prescaler. a block diagram of the type b timer is shown in figure 13-1 . timer3 and timer5 are type c timers with the following specific features: a type c timer can be concatenated with a type b timer to form a 32-bit timer at least one type c timer has the ability to trigger an analog-to-digital conversion. the external clock input (txck) is always syn- chronized to the internal device clock and the clock synchronization is performed before the prescaler a block diagram of the type c timer is shown in figure 13-2 . figure 13-1: type b timer bl ock diagram (x = 2 or 4) figure 13-2: type c timer block diagram (x = 3 or 5) note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 11. timers (ds70205) of the dspic33f/pic24h family refer- ence manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. prescaler (/n) tgate tcs 00 10 x1 tmrx comparator prx tgate set txif flag 0 1 sync tckps<1:0> equal reset txck gate sync f cy falling edge detect prescaler (/n) tckps<1:0> prescaler (/n) gate sync tgate tcs 00 10 x1 tmrx comparator prx f cy tgate falling edge detect set txif flag 0 1 sync tckps<1:0> equal reset txck adc soc trigger prescaler (/n) tckps<1:0> downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 194 ? 2007-2012 microchip technology inc. the timer2/3 and timer4/5 modules can operate in one of the following modes: timer mode gated timer mode synchronous counter mode in timer and gated timer modes, the input clock is derived from the internal instruction cycle clock (f cy ). in synchronous counter mode, the input clock is derived from the external clock input at txck pin. the timer modes are determined by the following bits: tcs (txcon<1>): timer clock source control bit tgate (txcon<6>): timer gate control bit timer control bit settings for different operating modes are given in the table 13-1 . table 13-1: timer mode settings 13.1 16-bit operation to configure any of the timers for individual 16-bit operation: 1. clear the t32 bit corresponding to that timer. 2. select the timer prescaler ratio using the tckps<1:0> bits. 3. set the clock and gating modes using the tcs and tgate bits. 4. load the timer period value into the prx register. 5. if interrupts are required, set the interrupt enable bit, txie. use the priority bits, txip<2:0>, to set the interrupt priority. 6. set the ton bit. 13.2 32-bit operation a 32-bit timer module can be formed by combining a type b and a type c 16-bit timer module. for 32-bit timer operation, the t32 control bit in the type b timer control register (txcon<3>) must be set. the type c timer holds the most significant word (msw) and the type b timer holds the least significant word (lsw) for 32-bit operation. when configured for 32-bit operation, only the type b timer control register (txc on) bits are required for setup and control. type c timer control register bits are ignored (except tsidl bit). for interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag and interrupt priority control bits of the type c timer. the interrupt control and status bits for the type b timer are ignored during 32-bit timer operation. the type b and type c timers that can be combined to form a 32-bit timer are listed in table 13-2 . table 13-2: 32-bit timer a block diagram representation of the 32-bit timer mod- ule is shown in figure 13-3 . the 32-bit timer module can operate in one of the following modes: timer mode gated timer mode synchronous counter mode to configure the features of timer2/3 or timer4/5 for 32-bit operation: 1. set the t32 control bit. 2. select the prescaler ra tio for timer2 or timer4 using the tckps<1:0> bits. 3. set the clock and gating modes using the corresponding tcs and tgate bits. 4. load the timer period value. pr3 or pr5 con- tains the most significant word of the value, while pr2 or pr4 contains the least significant word. 5. if interrupts are required, set the interrupt enable bits, t3ie or t5ie. us e the priority bits, t3ip<2:0> or t5ip<2:0> to set the interrupt pri- ority. while timer2 or timer4 controls the timer, the interrupt appears as a timer3 or timer5 interrupt. 6. set the corresponding ton bit. the timer value at any point is stored in the register pair, tmr3:tmr2 or tmr5:tmr4, which always contains the most significant word of the count, while tmr2 or tmr4 contains the least significant word. mode tcs tgate timer 00 gated timer 01 synchronous counter 1x note: only timer2 and timer3 can trigger a dma data transfer. type b timer (lsw) type c timer (msw) timer2 timer3 timer4 timer5 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 195 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 13-3: 32-bit timer block diagram 13.3 timer resources many useful resources related to timers are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 13.3.1 key resources section 11. timers (ds70205) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools prescaler (/n) tgate tcs 00 10 x1 tmrx prx tgate set tyif 0 1 sync tckps<1:0> equal txck gate sync f cy falling edge detect prescaler (/n) tckps<1:0> tmry comparator pry reset msw lsw tmryhld data bus <15:0> flag adc soc trigger note 1: adc trigger is available only on tmr3:tmr2 and tmr5:tmr2 32-bit timers. 2: timer x is a type b timer (x = 2 and 4). 3: timer y is a type c timer (y = 3 and 5). note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 196 ? 2007-2012 microchip technology inc. 13.4 timerx/y control registers register 13-1: txcon: timer control re gister (x = 2 or 4, y = 3 or 5) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton t s i d l bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate tckps<1:0> t32 t c s bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timerx on bit when t32 = 1 (in 32-bit timer mode): 1 = starts 32-bit tmrx:tmry timer pair 0 = stops 32-bit tmrx:tmry timer pair when t32 = 0 (in 16-bit timer mode): 1 = starts 16-bit timer 0 = stops 16-bit timer bit 14 unimplemented: read as 0 bit 13 tsidl: stop in idle mode bit 1 = discontinue timer operation when device enters idle mode 0 = continue timer operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timerx gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timerx input clock prescale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 t32: 32-bit timerx mode select bit 1 = tmrx and tmry form a 32-bit timer 0 = tmrx and tmry form separate 16-bit timer bit 2 unimplemented: read as 0 bit 1 tcs: timerx clock source select bit 1 = external clock from txck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 197 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 13-2: txcon: timer co ntrol register (x = 3 or 5) r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ton (2) t s i d l (1) bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 t g a t e (2) tckps<1:0> (2) t c s (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ton: timery on bit (2) 1 = starts 16-bit timer x 0 = stops 16-bit timer x bit 14 unimplemented: read as 0 bit 13 tsidl: stop in idle mode bit (1) 1 = discontinue timer operation when device enters idle mode 0 = continue timer operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 tgate: timer x gated time accumulation enable bit (2) when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation enabled 0 = gated time accumulation disabled bit 5-4 tckps<1:0>: timer x input clock prescale select bits (2) 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as 0 bit 1 tcs: timer x clock source select bit (2) 1 = external clock from txck pin 0 = internal clock (f osc /2) bit 0 unimplemented: read as 0 note 1: when 32-bit timer operation is enabled (t32 = 1 ) in the timer control regist er (txcon<3>), the tsidl bit must be cleared to operate th e 32-bit timer in idle mode. 2: when the 32-bit timer operation is enabled (t32 = 1 ) in the timer control register (txcon<3>), these bits have no effect. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 198 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 199 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 14.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 devices support up to four input capture channels. the input capture module captures the 16-bit value of the selected time base register when an event occurs at the icx pin. the events that cause a capture event are listed below in three categories: 1. simple capture event modes: - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin 2. capture timer value on every edge (rising and falling) 3. prescaler capture event modes: - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select one of two 16- bit timers (timer2 or time r3) for the time base. the selected timer can use either an internal or external clock. other operational features include: device wake-up from capture pin during cpu sleep and idle modes interrupt on input capture event 4-word fifo buffer for capture values - interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled use of input capture to provide additional sources of external interrupts figure 14-1: input capture block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 12. input capture (ds70198) of the dspic33f/pic24h family reference manual , which is avail- able from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: only ic1 and ic2 can trigger a dma data transfer. if dma data transfers are required, the fifo buffer size must be set to 1 (ici<1:0> = 00 ) note: an x in a signal, register or bit name denotes the number of the capture channel. fifo control icxbuf tmr2 tmr3 capture event /n fifo ici<1:0> icm<2:0> icm<2:0> 101 100 011 010 001 001 111 to cpu set flag icxif (in ifsx register) rising edge mode prescaler mode (4th rising edge) falling edge mode edge detection prescaler mode (16th rising edge) sleep/idle wake-up mode ictmr icx pin mode downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 200 ? 2007-2012 microchip technology inc. 14.1 input capture resources many useful resources related to input capture are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 14.1.1 key resources section 12. input capture (ds70198) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 201 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 14.2 input capture registers register 14-1: icxcon: input capture x control register (x = 1, 2, 7 or 8) u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 i c s i d l bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-0, hc r-0, hc r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 icsidl: input capture module stop in idle control bit 1 = input capture module halts in cpu idle mode 0 = input capture module continue s to operate in cpu idle mode bit 12-8 unimplemented: read as 0 bit 7 ictmr: input capture timer select bits 1 = tmr2 contents are captured on capture event 0 = tmr3 contents are captured on capture event bit 6-5 ici<1:0>: select number of captures per interrupt bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer empty status bit (read-only) 1 = input capture buffer is not empty, at least one more capture value can be read 0 = input capture buffer is empty bit 2-0 icm<2:0>: input capture mode select bits 111 = input capture functions as interrupt pin on ly when device is in sleep or idle mode (rising edge detect only, all other control bits are not applicable.) 110 = unused (module disabled) 101 = capture mode, every 16th rising edge 100 = capture mode, every 4th rising edge 011 = capture mode, every rising edge 010 = capture mode, every falling edge 001 = capture mode, every edge (rising and falling) (ici<1:0> bits do not control inte rrupt generation for this mode.) 000 = input capture module turned off downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 202 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 203 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 15.0 output compare the output compare module can select either timer2 or timer3 for its time ba se. the module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. the state of the output pi n changes when the timer value matches the compare register value. the output compare module generates either a single output pulse or a sequence of output pulses, by changing the state of the output pin on the compare match events. the output compare module can also generate interrupts on compare match events. the output compare module has multiple operating modes: active-low one-shot mode active-high one-shot mode toggle mode delayed one-shot mode continuous pulse mode pwm mode without fault protection pwm mode with fault protection figure 15-1: output compare module block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. output compare (ds70209) of the dspic33f/ pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. ocxr comparator output logic ocm<2:0> ocx set flag bit ocxif ocxrs mode select 3 0 1 octsel 0 1 16 16 ocfa tmr2 tmr2 q s r tmr3 tmr3 rollover rollover output logic output enable enable downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 204 ? 2007-2012 microchip technology inc. 15.1 output compare modes configure the output compare modes by setting the appropriate output compare mode bits (ocm<2:0>) in the output compare contro l register (ocxcon<2:0>). table 15-1 lists the different bit settings for the output compare modes. figure 15-2 illustrates the output compare operation for various modes. the user appli- cation must disable the associated timer when writing to the output compare control registers to avoid malfunctions. table 15-1: output compare modes figure 15-2: output compare operation note 1: only oc1 and oc2 can trigger a dma data transfer. 2: see section 13. output compare (ds70209) in the dspic33f/pic24h family reference manual for ocxr and ocxrs register restrictions. ocm<2:0> mode ocx pin initial state ocx interrupt generation 000 module disabled controlled by gpio register 001 active-low one-shot 0 ocx rising edge 010 active-high one-shot 1 ocx falling edge 011 toggle mode current output is maintained ocx rising and falling edge 100 delayed one-shot 0 ocx falling edge 101 continuous pulse mode 0 ocx falling edge 110 pwm mode without fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero no interrupt 111 pwm mode with fault protection 0 , if ocxr is zero 1 , if ocxr is non-zero ocfa falling edge for oc1 to oc4 ocxrs tmry ocxr timer is reset on period match continuous pulse mode (ocm = 101 ) pwm mode (ocm = 110 or 111 ) active-low one-shot (ocm = 001 ) active-high one-shot (ocm = 010 ) toggle mode (ocm = 011 ) delayed one-shot (ocm = 100 ) output compare mode enabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 205 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 15.2 output compare resources many useful resources related to output compare are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 15.2.1 key resources section 13. output compare (ds70209) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 206 ? 2007-2012 microchip technology inc. 15.3 output compare control register register 15-1: ocxcon: output compare x control register (x = 1, 2, 3 or 4) u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 o c s i d l bit 15 bit 8 u-0 u-0 u-0 r-0 hc r/w-0 r/w-0 r/w-0 r/w-0 ocflt octsel ocm<2:0> bit 7 bit 0 legend: hc = cleared in hardware hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 ocsidl: stop output compare in idle mode control bit 1 = output compare x halts in cpu idle mode 0 = output compare x continues to operate in cpu idle mode bit 12-5 unimplemented: read as 0 bit 4 ocflt: pwm fault condition status bit 1 = pwm fault condition has occurred (cleared in hardware only) 0 = no pwm fault condition has occurred (this bit is only used when ocm<2:0> = 111 .) bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for compare x 0 = timer2 is the clock source for compare x bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx, fault pin enabled 110 = pwm mode on ocx, fault pin disabled 101 = initialize ocx pin low, generate continuous output pulses on ocx pin 100 = initialize ocx pin low, generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high, compare event forces ocx pin low 001 = initialize ocx pin low, compare event forces ocx pin high 000 = output compare channel is disabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 207 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 16.0 serial peripheral interface (spi) the serial peripheral interface (spi) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices can be serial eeproms, shift regis- ters, display drivers, analog- to-digital converters, etc. the spi module is compatible with motorola ? spi and siop. each spi module consists of a 16-bit shift register, spixsr (where x = 1 or 2), used for shifting data in and out, and a buffer register, spix buf. a control register, spixcon, configures the module. additionally, a status register, spixstat, indi cates status conditions. the serial interface consists of 4 pins: sdix (serial data input) sdox (serial data output) sckx (shift clock input or output) ssx (active-low slave select). in master mode operation, sck is a clock output. in slave mode, it is a clock input. figure 16-1: spi module block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 18. serial peripheral interface (spi) (ds70206) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. internal data bus sdix sdox ssx sckx spixsr bit 0 shift control edge select f cy primary 1:1/4/16/64 enable prescaler sync spixbuf control transfer transfer write spixbuf read spixbuf 16 spixcon1<1:0>spixcon1<4:2> master clock clock control secondary prescaler 1:1 to 1:8 spixrxb spixtxb downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 208 ? 2007-2012 microchip technology inc. 16.1 spi helpful tips 1. in frame mode, if there is a possibility that the master may not be initialized before the slave: a) if frmpol (spixcon2<13>) = 1 , use a pull-down resistor on ssx . b) if frmpol = 0 , use a pull-up resistor on ssx . 2. in non-framed 3-wire mode, (i.e., not using ssx from a master): a) if ckp (spixcon1<6>) = 1 , always place a pull-up resistor on ssx . b) if ckp = 0 , always place a pull-down resistor on ssx . 3. frmen (spixcon2<15>) = 1 and ssen (spixcon1<7>) = 1 are exclusive and invalid. in frame mode, sckx is continuous and the frame sync pulse is active on the ssx pin, which indicates the start of a data frame. 4. in master mode only, set the smp bit (spixcon1<9>) to a 1 for the fastest spi data rate possible. the smp bit can only be set at the same time or after the msten bit (spixcon1<5>) is set. 5. to avoid invalid slave read data to the master, the users master software must guarantee enough time for slave software to fill its write buf- fer before the user application initiates a master write/read cycle. it is always advisable to pre- load the spixbuf transmit register in advance of the next master transaction cycle. spixbuf is transferred to the spi shift register and is empty once the data transmission begins. 16.2 spi resources many useful resources rela ted to spi are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 16.2.1 key resources section 18. serial peripheral interface (spi) (ds70206) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: this insures that the first frame transmission after initialization is not shifted or corrupted. note: this will insure that during power-up and initialization the master/slave will not lose sync due to an errant sck transition that would cause the slave to accumulate data shift errors for both transmit and receive appearing as corrupted data. note: not all third-party devices support frame mode timing. refer to the spi electrical characteristics for details. note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 209 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 16.3 spi control registers register 16-1: spixstat: spix status and control register r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 spien s p i s i d l bit 15 bit 8 u-0 r/c-0 u-0 u-0 u-0 u-0 r-0 r-0 spirov spitbf spirbf bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 spien: spix enable bit 1 = enables module and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables module bit 14 unimplemented: read as 0 bit 13 spisidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-7 unimplemented: read as 0 bit 6 spirov: receive overflow flag bit 1 = a new byte/word is completely received and discarded. the user software has not read the previous data in the spixbuf register 0 = no overflow has occurred bit 5-2 unimplemented: read as 0 bit 1 spitbf: spix transmit buffer full status bit 1 = transmit not yet started, spixtxb is full 0 = transmit started, spixtxb is empty automatically set in hardware when cpu writes spixbuf location, loading spixtxb. automatically cleared in hardware when spix modu le transfers data from spixtxb to spixsr. bit 0 spirbf: spix receive buffer full status bit 1 = receive complete, spixrxb is full 0 = receive is not comp lete, spixrxb is empty automatically set in hardware when spix transfers data from spixsr to spixrxb. automatically cleared in hardware when core reads spixbuf location, reading spixrxb. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 210 ? 2007-2012 microchip technology inc. register 16-2: spi x con1: spix control register 1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dissck dissdo mode16 smp cke (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen (3) ckp msten spre<2:0> (2) ppre<1:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 dissck: disable sckx pin bit (spi master modes only) 1 = internal spi clock is disabled, pin functions as i/o 0 = internal spi clock is enabled bit 11 dissdo: disable sdox pin bit 1 = sdox pin is not used by module; pin functions as i/o 0 = sdox pin is controlled by the module bit 10 mode16: word/byte communication select bit 1 = communication is word-wide (16 bits) 0 = communication is byte-wide (8 bits) bit 9 smp: spix data input sample phase bit master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode: smp must be cleared when spix is used in slave mode. bit 8 cke: spix clock edge select bit (1) 1 = serial output data changes on transition from active clock state to idle clock state (see bit 6) 0 = serial output data changes on transition from idle clock state to active clock state (see bit 6) bit 7 ssen: slave select enable bit (slave mode) (3) 1 = ssx pin used for slave mode 0 = ssx pin not used by module. pin controlled by port function bit 6 ckp: clock polarity select bit 1 = idle state for clock is a high le vel; active state is a low level 0 = idle state for clock is a low le vel; active state is a high level bit 5 msten: master mode enable bit 1 = master mode 0 = slave mode note 1: the cke bit is not used in the framed spi modes. program this bit to 0 for the framed spi modes (frmen = 1 ). 2: do not set both primary and secondary prescalers to the value of 1:1. 3: this bit must be cleared when frmen = 1 . downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 211 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 4-2 spre<2:0>: secondary prescale bits (master mode) (2) 111 = secondary prescale 1:1 110 = secondary prescale 2:1 000 = secondary prescale 8:1 bit 1-0 ppre<1:0>: primary prescale bits (master mode) (2) 11 = primary prescale 1:1 10 = primary prescale 4:1 01 = primary prescale 16:1 00 = primary prescale 64:1 register 16-2: spi x con1: spix control register 1 (continued) note 1: the cke bit is not used in the framed spi modes. program this bit to 0 for the framed spi modes (frmen = 1 ). 2: do not set both primary and secondary prescalers to the value of 1:1. 3: this bit must be cleared when frmen = 1 . downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 212 ? 2007-2012 microchip technology inc. register 16-3: spixcon2: spix control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 frmen spifsd frmpol bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 u-0 frmdly bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 frmen: framed spix support bit 1 = framed spix support enabled (ssx pin used as frame sync pulse input/output) 0 = framed spix support disabled bit 14 spifsd: frame sync pulse direction control bit 1 = frame sync pulse input (slave) 0 = frame sync pulse output (master) bit 13 frmpol: frame sync pulse polarity bit 1 = frame sync pulse is active-high 0 = frame sync pulse is active-low bit 12-2 unimplemented: read as 0 bit 1 frmdly: frame sync pulse edge select bit 1 = frame sync pulse coincides with first bit clock 0 = frame sync pulse precedes first bit clock bit 0 unimplemented: read as 0 this bit must not be set to 1 by the user application. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 213 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 17.0 inter-integrated circuit? (i 2 c?) the inter-integrated circuit (i 2 c) module provides complete hardware support for both slave and multi- master modes of the i 2 c serial communication standard, with a 16-bit interface. the i 2 c module has a 2-pin interface: the sclx pin is clock. the sdax pin is data. the i 2 c module offers the following key features: i 2 c interface supporting both master and slave modes of operation. i 2 c slave mode supports 7-bit and 10-bit addressing i 2 c master mode supports 7 and 10-bit addressing i 2 c port allows bidirectional transfers between master and slaves. serial clock synch ronization for i 2 c port can be used as a handshake mechanism to suspend and resume serial transfe r (sclrel control). i 2 c supports multi-master operation, detects bus collision and arbitrates accordingly. 17.1 operating modes the hardware fully implements all the master and slave functions of the i 2 c standard and fast mode specifications, as well as 7 and 10-bit addressing. the i 2 c module can operate either as a slave or a master on an i 2 c bus. the following types of i 2 c operation are supported: i 2 c slave operation with 7-bit addressing i 2 c slave operation with 10-bit addressing i 2 c master operation with 7-bit or 10-bit addressing for details about the communication sequence in each of these modes, refer to the dspic33f/pic24h family reference manual . please see the microchip website ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual chapters. note 1: this data sheet summ arizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 19. inter-integrated circuit? (i 2 c?) (ds70195) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for de vice-specific register and bit information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 214 ? 2007-2012 microchip technology inc. figure 17-1: i 2 c? block diagram ( x = 1) internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control t cy /2 start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 215 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 17.2 i 2 c resources many useful resources related to i 2 c are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 17.2.1 key resources section 11. inter-integrated circuit? (i 2 c?) (ds70195) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools 17.3 i 2 c registers i2cxcon and i2cxstat are control and status registers, respectively. the i2cxcon register is readable and writable. the lower six bits of i2cxstat are read-only. the remaining bits of the i2cstat are read/write: i2cxrsr is the shift register used for shifting data internal to the module and the user application has no access to it. i2cxrcv is the receive buffer and the register to which data bytes are written, or from which data bytes are read. i2cxtrn is the transmit register to which bytes are written during a transmit operation. the i2cxadd register holds the slave address. a status bit, add10, indicates 10-bit address mode. the i2cxbrg acts as the baud rate generator (brg) reload value. in receive operations, i2cxrsr and i2cxrcv together form a double-buffered receiver. when i2cxrsr receives a complete byte, it is transferred to i2cxrcv, and an interrupt pulse is generated. note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 216 ? 2007-2012 microchip technology inc. register 17-1: i2cxcon: i2cx control register r/w-0 u-0 r/w-0 r/w-1 hc r/w-0 r/w-0 r/w-0 r/w-0 i2cen i2csidl sclrel ipmien a10m disslw smen bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc r/w-0 hc gcen stren ackdt acken rcen pen rsen sen bit 7 bit 0 legend: u = unimplemented bit, read as 0 r = readable bit w = writable bit hs = set in hardware hc = cleared in hardware -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 i2cen: i2cx enable bit 1 = enables the i2cx module and configures the sdax and sclx pins as serial port pins 0 = disables the i2cx module. all i 2 c? pins are controlled by port functions bit 14 unimplemented: read as 0 bit 13 i2csidl: stop in idle mode bit 1 = discontinue module operation when device enters an idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write 0 to initiate stretch and write 1 to release clock). hardware clear at beginning of slave transmission. hard ware clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write 1 to release clock). hardware clear at beginning of slave transmission. bit 11 ipmien: intelligent peripheral management interface (ipmi) enable bit 1 = ipmi mode is enabled; all addresses acknowledged 0 = ipmi mode disabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds co mpliant with smbus specification 0 = disable smbus input thresholds bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 217 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the software initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax an d sclx pins and transmit ackdt data bit. hardware clear at end of master acknowledge sequence 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins . hardware clear at end of master stop sequence 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of master repeated start sequence 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins . hardware clear at end of master start sequence 0 = start condition not in progress register 17-1: i2cxcon: i2cx control register (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 218 ? 2007-2012 microchip technology inc. register 17-2: i2cxstat: i2cx status register r-0 hsc r-0 hsc u-0 u-0 u-0 r/c-0 hs r-0 hsc r-0 hsc ackstat trstat bcl gcstat add10 bit 15 bit 8 r/c-0 hs r/c-0 hs r-0 hsc r/c-0 hsc r/c-0 hsc r-0 hsc r-0 hsc r-0 hsc iwcol i2cov d_a p s r_w rbf tbf bit 7 bit 0 legend: u = unimplemented bit, read as 0 c = clear only bit r = readable bit w = writable bit hs = set in hardware hsc = hardware set/cleared -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ackstat: acknowledge status bit (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission . hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as 0 bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detec ted during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10 -bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cxrcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 219 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read C indicates data transfer is output from slave 0 = write C indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hard ware clear at completion of data transmission. register 17-2: i2cxstat: i2cx status register (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 220 ? 2007-2012 microchip technology inc. register 17-3: i2cxmsk: i2cx sl ave mode address mask register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 amsk9 amsk8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 amsk7 amsk6 amsk5 amsk4 amsk3 amsk2 amsk1 amsk0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 unimplemented: read as 0 bit 9-0 amskx: mask for address bit x select bit 1 = enable masking for bit x of incoming message address; bit match not requ ired in this position 0 = disable masking for bit x; bit match required in this position downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 221 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 18.0 universal asynchronous receiver transmitter (uart) the universal asynchronous receiver transmitter (uart) module is one of the serial i/o modules available in the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 device family. the uart is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, lin 2.0, rs-232 and rs-485 interfaces. the module also supports a hardware flow control option with the uxcts and uxrts pins and also includes an irda ? encoder and decoder. the primary features of the uart module are: full-duplex, 8-bit or 9-bit data transmission through the uxtx and uxrx pins even, odd or no parity options (for 8-bit data) one or two stop bits hardware flow control option with uxcts and uxrts pins fully integrated baud rate generator with 16-bit prescaler baud rates ranging from 10 mbps to 38 bps at 40 mips 4-deep first-in first-out (fifo) transmit data buffer 4-deep fifo receive data buffer parity, framing and buffer overrun error detection support for 9-bit mode with address detect (9th bit = 1 ) transmit and receive interrupts a separate interrupt for all uart error conditions loopback mode for diagnostic support support for sync and break characters support for automatic baud rate detection irda ? encoder and decoder logic 16x baud clock output for irda ? support a simplified block diagram of the uart module is shown in figure 18-1 . the uart module consists of these key hardware elements: baud rate generator asynchronous transmitter asynchronous receiver figure 18-1: uart simplified block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. uart (ds70188) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note 1: both uart1 and uart2 can trigger a dma data transfer. 2: if dma transfers are required, the uart tx/rx fi fo buffer must be set to a size of 1 byte/word (i.e., utxisel<1:0> = 00 and urxisel<1:0> = 00 ). uxrx hardware flow control uart receiver uart transmitter uxtx baud rate generator uxrts /blckx irda ? uxcts downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 222 ? 2007-2012 microchip technology inc. 18.1 uart helpful tips 1. in multi-node direct-connect uart networks, uart receive inputs react to the complementary logic level defined by the urxinv bit (uxmode<4>), which defines the idle state, the default of which is logic high, (i.e., urxinv = 0 ). because remote devices do not initialize at the same time , it is likely that one of the devices, because the rx line is floating, will trigger a start bit detection and will cause the first byte received after the device has been ini- tialized to be invalid. to avoid this situation, the user should use a pull-up or pull-down resistor on the rx pin depending on the value of the urxinv bit. a) if urxinv = 0 , use a pull-up resistor on the rx pin. b) if urxinv = 1 , use a pull-down resistor on the rx pin. 2. the first character received on a wake-up from sleep mode caused by activity on the uxrx pin of the uart module will be invalid. in sleep mode, peripheral clocks are disabled. by the time the oscillator system has restarted and stabilized from sleep mode, the baud rate bit sampling clock relative to the incoming uxrx bit timing is no longer synchronized, resulting in the first character being invalid. this is to be expected. 18.2 uart resources many useful resources related to uart are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 18.2.1 key resources section 17. uart (ds70188) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 223 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 18.3 uart control registers register 18-1: uxmode: uart x mode register r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uarten (1) usidl iren (2) rtsmd u e n < 1 : 0 > bit 15 bit 8 r/w-0 hc r/w-0 r/w-0 hc r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud urxinv brgh pdsel<1:0> stsel bit 7 bit 0 legend: hc = hardware cleared r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 uarten: uartx enable bit (1) 1 = uartx is enabled; all uartx pins are controlled by uartx as defined by uen<1:0> 0 = uartx is disabled; all uartx pins are controlled by port latches; uartx power consumption minimal bit 14 unimplemented: read as 0 bit 13 usidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 iren: irda ? encoder and decoder enable bit (2) 1 =irda ? encoder and decoder enabled 0 =irda ? encoder and decoder disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 =uxrts pin in simplex mode 0 =uxrts pin in flow control mode bit 10 unimplemented: read as 0 bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and bclk pins are enabled and used; uxcts pin controlled by port latches 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin controlled by port latches 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /bclk pins controlled by port latches bit 7 wake: wake-up on start bit detect during sleep mode enable bit 1 = uartx continues to sample the uxrx pin; interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = no wake-up enabled bit 6 lpback: uartx loopback mode select bit 1 = enable loopback mode 0 = loopback mode is disabled bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next character C requires reception of a sync field (55h) before other data; cleared in hardware upon completion 0 = baud rate measurement disabled or completed note 1: refer to section 17. uart (ds70188) in the dspic33f/pic24h family reference manual for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 224 ? 2007-2012 microchip technology inc. bit 4 urxinv: receive polarity inversion bit 1 = uxrx idle state is 0 0 = uxrx idle state is 1 bit 3 brgh: high baud rate enable bit 1 = brg generates 4 clocks per bit period (4x baud clock, high-speed mode) 0 = brg generates 16 clocks per bit period (16x baud clock, standard mode) bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop bit selection bit 1 = two stop bits 0 = one stop bit register 18-1: uxmode: uart x mode register (continued) note 1: refer to section 17. uart (ds70188) in the dspic33f/pic24h family reference manual for information on enabling the uart module for receive or transmit operation. 2: this feature is only available for the 16x brg mode (brgh = 0 ). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 225 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 18-2: u x sta: uart x status and control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 hc r/w-0 r-0 r-1 utxisel1 utxinv utxisel0 utxbrk utxen (1) utxbf trmt bit 15 bit 8 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/c-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda bit 7 bit 0 legend: hc = hardware cleared c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15,13 utxisel<1:0>: transmission interrupt mode selection bits 11 = reserved; do not use 10 = interrupt when a character is transferred to the transmit shift register, and as a result, the transmit buffer becomes empty 01 = interrupt when the last character is shifted ou t of the transmit shift register; all transmit operations are completed 00 = interrupt when a character is transferred to t he transmit shift register (this implies there is at least one character open in the transmit buffer) bit 14 utxinv: transmit polarity inversion bit if iren = 0 : 1 = uxtx idle state is 0 0 = uxtx idle state is 1 if iren = 1 : 1 =irda ? encoded uxtx idle state is 1 0 =irda ? encoded uxtx idle state is 0 bit 12 unimplemented: read as 0 bit 11 utxbrk: transmit break bit 1 = send sync break on next transmission C start bit, followed by twelve 0 bits, followed by stop bit; cleared by hardware upon completion 0 = sync break transmission disabled or completed bit 10 utxen: transmit enable bit (1) 1 = transmit enabled, uxtx pin controlled by uartx 0 = transmit disabled, any pending transmission is abo rted and buffer is reset. uxtx pin controlled by port bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at least one more character can be written bit 8 trmt: transmit shift register empty bit (read-only) 1 = transmit shift register is em pty and transmit buffer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmission is in progress or queued bit 7-6 urxisel<1:0>: receive interrupt mode selection bits 11 = interrupt is set on uxrsr transfer making the receive buffer full (i.e., has 4 data characters) 10 = interrupt is set on uxrsr transfer making the re ceive buffer 3/4 full (i.e., has 3 data characters) 0x = interrupt is set when any character is receiv ed and transferred from the uxrsr to the receive buffer. receive buffer has one or more characters. note 1: refer to section 17. uart (ds70188) in the dspic33f/pic24h family reference manual for information on enabling the uart module for transmit operation. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 226 ? 2007-2012 microchip technology inc. bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode enabled. if 9-bit mode is not selected, this does not take effect 0 = address detect mode disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = receiver is active bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current ch aracter (character at the top of the receive fifo) 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character (character at the top of the receive fifo) 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit (read/clear only) 1 = receive buffer has overflowed 0 = receive buffer has not overflowed. clearing a previously set oerr bit ( 1 0 transition) resets the receiver buffer and t he uxrsr to the empty state. bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 18-2: u x sta: uart x status and control register (continued) note 1: refer to section 17. uart (ds70188) in the dspic33f/pic24h family reference manual for information on enabling the uart module for transmit operation. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 227 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 19.0 enhanced can (ecan?) module 19.1 overview the enhanced controller area network (ecan?) module is a serial interface, useful for communicating with other can modules or microcontroller devices. this interface/protocol was designed to allow commu- nications within noisy environments. the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices contain up to two ecan modules. the ecan module is a communication controller implementing the can 2.0 a/b protocol, as defined in the bosch can specificatio n. the module supports can 1.2, can 2.0a, can 2.0b passive and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader can refer to the bosch can specification for further details. the module features are as follows: implementation of the can protocol, can 1.2, can 2.0a and can 2.0b standard and extended data frames 0-8 bytes data length programmable bit rate up to 1 mbit/sec automatic response to remote transmission requests up to eight transmit buffers with application speci- fied prioritization and abort capability (each buffer can contain up to 8 bytes of data) up to 32 receive buffers (each buffer can contain up to 8 bytes of data) up to 16 full (standard/extended identifier) acceptance filters three full acceptance filter masks devicenet? addressing support programmable wake-up functionality with integrated low-pass filter programmable loopback mode supports self-test operation signaling via interrupt capabilities for all can receiver and transm itter error states programmable clock source programmable link to input capture module (ic2 for can1) for time-stamping and network synchroniza- tion low-power sleep and idle mode the can bus module consists of a protocol engine and message buffering/control. the can protocol engine handles all functions for receiving and transmitting messages on the can bus. messages are transmitted by first loading the appropriate data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the receive registers. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 21. enhanced control- ler area network (ecan?) (ds70185) of the dspic33f/pic24h family refer- ence manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 228 ? 2007-2012 microchip technology inc. 19.2 frame types the ecan module transmits various types of frames which include data messages, or remote transmission requests initiated by the user , as other frames that are automatically generated for control purposes. the following frame types are supported: standard data frame: a standard data frame is generated by a node when the node wishes to transmit data. it includes an 11-bit standard identifier (sid), but not an 18- bit extended identifier (eid). extended data frame: an extended data frame is similar to a standard data frame, but includes an extended identifier as well. remote frame: it is possible for a destination node to request the data from the source. for this purpose, the destination node sends a remote frame with an identifier that matches the identifier of the required data frame. the appropriate data source node sends a data frame as a response to this remote request. error frame: an error frame is generated by any node that detects a bus error. an error frame consists of two fields: an error flag field and an error delimiter field. overload frame: an overload frame can be generated by a node as a result of two conditions. first, the node detects a dominant bit during interframe space which is an illegal condition. second, due to internal condi- tions, the node is not yet able to start reception of the next message. a node can generate a maxi- mum of 2 sequential overload frames to delay the start of the next message. interframe space: interframe space separates a proceeding frame (of whatever type) from a following data or remote frame. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 229 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 19-1: ecan? module block diagram message assembly can protocol engine c1tx buffer c1rx rxf14 filter rxf13 filter rxf12 filter rxf11 filter rxf10 filter rxf9 filter rxf8 filter rxf7 filter rxf6 filter rxf5 filter rxf4 filter rxf3 filter rxf2 filter rxf1 filter rxf0 filter transmit byte sequencer rxm1 mask rxm0 mask control configuration logic cpu bus interrupts trb0 tx/rx buffer control register dma controller rxf15 filter rxm2 mask trb7 tx/rx buffer control register trb6 tx/rx buffer control register trb5 tx/rx buffer control register trb4 tx/rx buffer control register trb3 tx/rx buffer control register trb2 tx/rx buffer control register trb1 tx/rx buffer control register downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 230 ? 2007-2012 microchip technology inc. 19.3 modes of operation the ecan module can operate in one of several operation modes selected by the user. these modes include: initialization mode disable mode normal operation mode listen only mode listen all messages mode loopback mode modes are requested by se tting the reqop<2:0> bits (cictrl1<10:8>). entry into a mode is acknowledged by monitoring the opmode<2:0> bits (cictrl1<7:5>). the module does not change the mode and the opmode bits until a change in mode is acceptable, generally during bus idle time, which is defined as at least 11 consecutive recessive bits. 19.3.1 initialization mode in the initialization mode, the module does not transmit or receive. the error counters are cleared and the inter- rupt flags remain unchanged. the user application has access to configuration registers that are access restricted in other modes. the module protects the user from accidentally violati ng the can protocol through programming errors. all registers which control the configuration of the module cannot be modified while the module is on-line. the ecan module is not allowed to enter the configuration mode while a transmission is taking place. the configuration mode serves as a lock to protect the following registers: all module control registers baud rate and interrupt configuration registers bus timing registers identifier acceptance filter registers identifier acceptance mask registers 19.3.2 disable mode in disable mode, the module does not transmit or receive. the module has the ability to set the wakif bit due to bus activity, however, any pending interrupts remains and the e rror counters retains their value. if the reqop<2:0> bits (cictrl1<10:8>) = 001 , the module enters the module disable mode. if the module is active, the module waits for 11 recessive bits on the can bus, detect that condition as an idle bus, then accept the module disable command. when the opmode<2:0> bits (cictrl1<7:5>) = 001 , that indicates whether the module successfully went into module disable mode. the i/o pins reverts to no rmal i/o function when the module is in the module disable mode. the module can be programmed to apply a low-pass filter function to the cirx i nput line while the module or the cpu is in sleep mode. the wakfil bit (cicfg2<14>) enables or disables the filter. 19.3.3 normal operation mode normal operation mode is selected when reqop<2:0> = 000 . in this mode, the module is activated and the i/o pins assumes the can bus functions. the module transmits and receive can bus messages via the citx and cirx pins. 19.3.4 listen only mode if the listen only mode is activated, the module on the can bus is passive. the tran smitter buffers revert to the port i/o function. the receive pins remain inputs. for the receiver, no error flags or acknowledge signals are sent. the error counters are deactivated in this state. the listen only mode can be used for detecting the baud rate on the can bus. to use this, it is necessary that there are at least two further nodes that communicate with each other. 19.3.5 listen all messages mode the module can be set to ignore all errors and receive any message. the listen all messages mode is acti- vated by setting reqop<2:0> = 111 . in this mode, the data which is in the message assembly buffer, until the time an error occurred, is copied in the receive buf- fer and can be read via the cpu interface. 19.3.6 loopback mode if the loopback mode is activated, the module con- nects the internal transmit signal to the internal receive signal at the module boundary. the transmit and receive pins revert to their port i/o function. note: typically, if the ecan module is allowed to transmit in a particular mode of operation and a transmission is requested immedi- ately after the ecan module has been placed in that mode of operation, the mod- ule waits for 11 consecutive recessive bits on the bus before starting transmission. if the user switches to disable mode within this 11-bit period, then this transmission is aborted and the corr esponding txabt bit is set and txreq bit is cleared. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 231 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 19.4 ecan resources many useful resources related to ecan are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 19.4.1 key resources section 21. enhanced controller area network (ecan?) (ds70185) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 232 ? 2007-2012 microchip technology inc. 19.5 ecan control registers register 19-1: cictrl1: ecan? control register 1 u-0 u-0 r/w-0 r/w-0 r-0 r/w-1 r/w-0 r/w-0 csidl abat reqop<2:0> bit 15 bit 8 r-1 r-0 r-0 u-0 r/w-0 u-0 u-0 r/w-0 opmode<2:0> c a n c a p w i n bit 7 bit 0 legend: r = bit is reserved r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 csidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 abat: abort all pending transmissions bit 1 = signal all transmit buffers to abort transmission. 0 = module will clear this bit when all transmissions are aborted bit 11 reserved: do not use bit 10-8 reqop<2:0>: request operation mode bits 111 = set listen all messages mode 110 = reserved 101 = reserved 100 = set configuration mode 011 = set listen only mode 010 = set loopback mode 001 = set disable mode 000 = set normal operation mode bit 7-5 opmode<2:0> : operation mode bits 111 = module is in listen all messages mode 110 = reserved 101 = reserved 100 = module is in configuration mode 011 = module is in listen only mode 010 = module is in loopback mode 001 = module is in disable mode 000 = module is in normal operation mode bit 4 unimplemented: read as 0 bit 3 cancap: can message receive timer capture event enable bit 1 = enable input capture based on can message receive 0 = disable can capture bit 2-1 unimplemented: read as 0 bit 0 win: sfr map window select bit 1 = use filter window 0 = use buffer window downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 233 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-2: cictrl2: ecan? control register 2 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 dncnt<4:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 unimplemented: read as 0 bit 4-0 dncnt<4:0>: devicenet? filter bit number bits 10010-11111 = invalid selection 10001 = compare up to data byte 3, bit 6 with eid<17> 00001 = compare up to data byte 1, bit 7 with eid<0> 00000 = do not compare data bytes downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 234 ? 2007-2012 microchip technology inc. register 19-3: civec: ecan? interrupt code register u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 filhit<4:0> bit 15 bit 8 u-0 r-1 r-0 r-0 r-0 r-0 r-0 r-0 i c o d e < 6 : 0 > bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 filhit<4:0>: filter hit number bits 10000-11111 = reserved 01111 = filter 15 00001 = filter 1 00000 = filter 0 bit 7 unimplemented: read as 0 bit 6-0 icode<6:0>: interrupt flag code bits 1000101-1111111 = reserved 1000100 = fifo almost full interrupt 1000011 = receiver overflow interrupt 1000010 = wake-up interrupt 1000001 = error interrupt 1000000 = no interrupt 0010000-0111111 = reserved 0001111 = rb15 buffer interrupt 0001001 = rb9 buffer interrupt 0001000 = rb8 buffer interrupt 0000111 = trb7 buffer interrupt 0000110 = trb6 buffer interrupt 0000101 = trb5 buffer interrupt 0000100 = trb4 buffer interrupt 0000011 = trb3 buffer interrupt 0000010 = trb2 buffer interrupt 0000001 = trb1 buffer interrupt 0000000 = trb0 buffer interrupt downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 235 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-4: cifctrl: ecan? fifo control register r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 dmabs<2:0> bit 15 bit 8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 fsa<4:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 dmabs<2:0>: dma buffer size bits 111 = reserved 110 = 32 buffers in dma ram 101 = 24 buffers in dma ram 100 = 16 buffers in dma ram 011 = 12 buffers in dma ram 010 = 8 buffers in dma ram 001 = 6 buffers in dma ram 000 = 4 buffers in dma ram bit 12-5 unimplemented: read as 0 bit 4-0 fsa<4:0>: fifo area starts with buffer bits 11111 = read buffer rb31 11110 = read buffer rb30 00001 = tx/rx buffer trb1 00000 = tx/rx buffer trb0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 236 ? 2007-2012 microchip technology inc. register 19-5: cififo: e can? fifo status register u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 fbp<5:0> bit 15 bit 8 u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 fnrb<5:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13-8 fbp<5:0>: fifo buffer pointer bits 011111 = rb31 buffer 011110 = rb30 buffer 000001 = trb1 buffer 000000 = trb0 buffer bit 7-6 unimplemented: read as 0 bit 5-0 fnrb<5:0>: fifo next read buffer pointer bits 011111 = rb31 buffer 011110 = rb30 buffer 000001 = trb1 buffer 000000 = trb0 buffer downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 237 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-6: ciintf: ec an? interrupt flag register u-0 u-0 r-0 r-0 r-0 r-0 r-0 r-0 txbo txbp rxbp txwar rxwar ewarn bit 15 bit 8 r/c-0 r/c-0 r/c-0 u-0 r/c-0 r/c-0 r/c-0 r/c-0 ivrif wakif errif fifoif rbovif rbif tbif bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 txbo: transmitter in error state bus off bit 1 = transmitter is in bus off state 0 = transmitter is not in bus off state bit 12 txbp: transmitter in error state bus passive bit 1 = transmitter is in bus passive state 0 = transmitter is not in bus passive state bit 11 rxbp: receiver in error state bus passive bit 1 = receiver is in bus passive state 0 = receiver is not in bus passive state bit 10 txwar: transmitter in error state warning bit 1 = transmitter is in error warning state 0 = transmitter is not in error warning state bit 9 rxwar: receiver in error state warning bit 1 = receiver is in error warning state 0 = receiver is not in error warning state bit 8 ewarn: transmitter or receiver in error state warning bit 1 = transmitter or receiver is in error state warning state 0 = transmitter or receiver is not in error state warning state bit 7 ivrif: invalid message received interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 6 wakif: bus wake-up activity interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 5 errif: error interrupt flag bit (multiple sources in ciintf< 13:8> register) 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 4 unimplemented: read as 0 bit 3 fifoif: fifo almost full interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 2 rbovif: rx buffer overflow interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 1 rbif: rx buffer interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred bit 0 tbif: tx buffer interrupt flag bit 1 = interrupt request has occurred 0 = interrupt request has not occurred downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 238 ? 2007-2012 microchip technology inc. register 19-7: ciinte: ecan? interrupt enable register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ivrie wakie errie fifoie rbovie rbie tbie bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7 ivrie: invalid message received interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 6 wakie: bus wake-up activity interrupt flag bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 5 errie: error interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 4 unimplemented: read as 0 bit 3 fifoie: fifo almost full interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 2 rbovie: rx buffer overflow interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 1 rbie: rx buffer interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled bit 0 tbie: tx buffer interrupt enable bit 1 = interrupt request enabled 0 = interrupt request not enabled downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 239 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-8: ciec: ecan? tran smit/receive error count register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 terrcnt<7:0> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rerrcnt<7:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 terrcnt<7:0>: transmit error count bits bit 7-0 rerrcnt<7:0>: receive error count bits register 19-9: cicfg1: ecan? b aud rate configuration register 1 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw<1:0> brp<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-6 sjw<1:0>: synchronization jump width bits 11 = length is 4 x t q 10 = length is 3 x t q 01 = length is 2 x t q 00 = length is 1 x t q bit 5-0 brp<5:0>: baud rate prescaler bits 11 1111 = t q = 2 x 64 x 1/f can 00 0010 = t q = 2 x 3 x 1/f can 00 0001 = t q = 2 x 2 x 1/f can 00 0000 = t q = 2 x 1 x 1/f can downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 240 ? 2007-2012 microchip technology inc. register 19-10: cicfg2: ecan? b aud rate configuration register 2 u-0 r/w-x u-0 u-0 u-0 r/w-x r/w-x r/w-x wakfil seg2ph<2:0> bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x seg2phts sam seg1ph <2:0> prseg<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 wakfil: select can bus line filter for wake-up bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 13-11 unimplemented: read as 0 bit 10-8 seg2ph<2:0>: phase segment 2 bits 111 = length is 8 x t q 000 = length is 1 x t q bit 7 seg2phts: phase segment 2 time select bit 1 = freely programmable 0 = maximum of seg1ph bits or information pr ocessing time (ipt), whichever is greater bit 6 sam: sample of the can bus line bit 1 = bus line is sampled three times at the sample point 0 = bus line is sampled once at the sample point bit 5-3 seg1ph<2:0>: phase segment 1 bits 111 = length is 8 x t q 000 = length is 1 x t q bit 2-0 prseg<2:0>: propagation time segment bits 111 = length is 8 x t q 000 = length is 1 x t q downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 241 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-11: cifen1: ecan? acceptance filter enable register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flten15 flten14 flten13 flten12 flten11 flten10 flten9 flten8 bit 15 bit 8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 flten7 flten6 flten5 flten4 flten3 flten2 flten1 flten0 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 fltenn: enable filter n to accept messages bits 1 = enable filter n 0 = disable filter n register 19-12: cibufpnt1: ecan? filter 0-3 buffer pointer register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f3bp<3:0> f2bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f1bp<3:0> f0bp<3:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 f3bp<3:0>: rx buffer mask for filter 3 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f2bp<3:0>: rx buffer mask for filter 2 (same values as bit 15-12) bit 7-4 f1bp<3:0>: rx buffer mask for filter 1 (same values as bit 15-12) bit 3-0 f0bp<3:0>: rx buffer mask for filter 0 (same values as bit 15-12) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 242 ? 2007-2012 microchip technology inc. register 19-13: cibufpnt2: ecan? filter 4-7 buffer pointer register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f7bp<3:0> f6bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f5bp<3:0> f4bp<3:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 f7bp<3:0>: rx buffer mask for filter 7 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f6bp<3:0>: rx buffer mask for filter 6 (same values as bit 15-12) bit 7-4 f5bp<3:0>: rx buffer mask for filter 5 (same values as bit 15-12) bit 3-0 f4bp<3:0>: rx buffer mask for filter 4 (same values as bit 15-12) register 19-14: cibufpnt3: ecan? fi lter 8-11 buffer pointer register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f11bp<3:0> f10bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f9bp<3:0> f8bp<3:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 f11bp<3:0>: rx buffer mask for filter 11 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f10bp<3:0>: rx buffer mask for filter 10 (same values as bit 15-12) bit 7-4 f9bp<3:0>: rx buffer mask for filter 9 (same values as bit 15-12) bit 3-0 f8bp<3:0>: rx buffer mask for filter 8 (same values as bit 15-12) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 243 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-15: cibufpnt4: ecan? filter 12-15 buffer pointer register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f15bp<3:0> f14bp<3:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f13bp<3:0> f12bp<3:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 f15bp<3:0>: rx buffer mask for filter 15 1111 = filter hits received in rx fifo buffer 1110 = filter hits received in rx buffer 14 0001 = filter hits received in rx buffer 1 0000 = filter hits received in rx buffer 0 bit 11-8 f14bp<3:0>: rx buffer mask for filter 14 (same values as bit 15-12) bit 7-4 f13bp<3:0>: rx buffer mask for filter 13 (same values as bit 15-12) bit 3-0 f12bp<3:0>: rx buffer mask for filter 12 (same values as bit 15-12) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 244 ? 2007-2012 microchip technology inc. register 19-16: cirxfnsid: ecan? accepta nce filter standard identifier register n (n = 0-15) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 15 bit 8 r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 e x i d e e i d 1 7e i d 1 6 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 sid<10:0>: standard identifier bits 1 = message address bit sidx must be 1 to match filter 0 = message address bit sidx must be 0 to match filter bit 4 unimplemented: read as 0 bit 3 exide: extended identifier enable bit if mide = 1 : 1 = match only messages with extended identifier addresses 0 = match only messages with standard identifier addresses if mide = 0 : ignore exide bit. bit 2 unimplemented: read as 0 bit 1-0 eid<17:16>: extended identifier bits 1 = message address bit eidx must be 1 to match filter 0 = message address bit eidx must be 0 to match filter downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 245 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-17: cirxfneid: ecan? acceptance filter extended identifier register n (n = 0-15) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 eid<15:0>: extended identifier bits 1 = message address bit eidx must be 1 to match filter 0 = message address bit eidx must be 0 to match filter register 19-18: cifmsksel1: ecan? filter 7-0 mask selection register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f7msk<1:0> f6msk<1:0> f5msk<1:0> f4msk<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f3msk<1:0> f2msk<1:0> f1msk<1:0> f0msk<1:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 f7msk<1:0>: mask source for filter 7 bit 11 = no mask 10 = acceptance mask 2 registers contain mask 01 = acceptance mask 1 registers contain mask 00 = acceptance mask 0 registers contain mask bit 13-12 f6msk<1:0>: mask source for filter 6 bit (same values as bit 15-14) bit 11-10 f5msk<1:0>: mask source for filter 5 bit (same values as bit 15-14) bit 9-8 f4msk<1:0>: mask source for filter 4 bit (same values as bit 15-14) bit 7-6 f3msk<1:0>: mask source for filter 3 bit (same values as bit 15-14) bit 5-4 f2msk<1:0>: mask source for filter 2 bit (same values as bit 15-14) bit 3-2 f1msk<1:0>: mask source for filter 1 bit (same values as bit 15-14) bit 1-0 f0msk<1:0>: mask source for filter 0 bit (same values as bit 15-14) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 246 ? 2007-2012 microchip technology inc. register 19-19: cifmsksel2: ecan? filter 15-8 mask selection register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f15msk<1:0> f14msk<1:0> f13msk<1:0> f12msk<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 f11msk<1:0> f10msk<1:0> f9msk<1:0> f8msk<1:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 f15msk<1:0>: mask source for filter 15 bit 11 = no mask 10 = acceptance mask 2 registers contain mask 01 = acceptance mask 1 registers contain mask 00 = acceptance mask 0 registers contain mask bit 13-12 f14msk<1:0>: mask source for filter 14 bit (same values as bit 15-14) bit 11-10 f13msk<1:0>: mask source for filter 13 bit (same values as bit 15-14) bit 9-8 f12msk<1:0>: mask source for filter 12 bit (same values as bit 15-14) bit 7-6 f11msk<1:0>: mask source for filter 11 bit (same values as bit 15-14) bit 5-4 f10msk<1:0>: mask source for filter 10 bit (same values as bit 15-14) bit 3-2 f9msk<1:0>: mask source for filter 9 bit (same values as bit 15-14) bit 1-0 f8msk<1:0>: mask source for filter 8 bit (same values as bit 15-14) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 247 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-20: cirxmnsid: ecan? acceptance filter mask standard identifier register n (n = 0-2) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 15 bit 8 r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 m i d e e i d 1 7e i d 1 6 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-5 sid<10:0>: standard identifier bits 1 = include bit sidx in filter comparison 0 = bit sidx is dont care in filter comparison bit 4 unimplemented: read as 0 bit 3 mide: identifier receive mode bit 1 = match only message types (standard or extended address) that correspond to exide bit in filter 0 = match either standard or extended address message if filters match (i.e., if (filter sid) = (me ssage sid) or if (filter si d/eid) = (message sid/eid)) bit 2 unimplemented: read as 0 bit 1-0 eid<17:16>: extended identifier bits 1 = include bit eidx in filter comparison 0 = bit eidx is dont care in filter comparison register 19-21: cirxmneid: ecan? acceptance filter mask extended identifier register n (n = 0-2) r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 eid<15:0>: extended identifier bits 1 = include bit eidx in filter comparison 0 = bit eidx is dont care in filter comparison downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 248 ? 2007-2012 microchip technology inc. register 19-22: cirxful1: ecan ? receive buffer full register 1 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful15 rxful14 rxful13 rxful12 rxful11 rxful10 rxful9 rxful8 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful7 rxful6 rxful5 rxful4 rxful3 rxful2 rxful1 rxful0 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 rxful<15:0>: receive buffer n full bits 1 = buffer is full (set by module) 0 = buffer is empty register 19-23: cirxful2: ecan ? receive buffer full register 2 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful31 rxful30 rxful29 rxful28 rxful27 rxful26 rxful25 rxful24 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxful23 rxful22 rxful21 rxful20 rxful19 rxful18 rxful17 rxful16 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 rxful<31:16>: receive buffer n full bits 1 = buffer is full (set by module) 0 = buffer is empty downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 249 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 19-24: cirxovf1: ecan? re ceive buffer overflow register 1 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf15 rxovf14 rxovf13 rxovf12 rxovf11 rxovf10 rxovf9 rxovf8 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf7 rxovf6 rxovf5 rxovf4 rxovf3 rxovf2 rxovf1 rxovf0 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 rxovf<15:0>: receive buffer n overflow bits 1 = module attempted to write to a full buffer (set by module) 0 = no overflow condition register 19-25: cirxovf2: ecan? re ceive buffer overflow register 2 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf31 rxovf30 rxovf29 rxovf28 rxovf27 rxovf26 rxovf25 rxovf24 bit 15 bit 8 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 r/c-0 rxovf23 rxovf22 rxovf21 rxovf20 rxovf19 rxovf18 rxovf17 rxovf16 bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 rxovf<31:16>: receive buffer n overflow bits 1 = module attempted to write to a full buffer (set by module) 0 = no overflow condition downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 250 ? 2007-2012 microchip technology inc. register 19-26: citrmncon: ecan? tx/rx buffer m control register (m = 0,2,4,6; n = 1,3,5,7) r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txenn txabtn txlarbn txerrn txreqn rtrenn txnpri<1:0> bit 15 bit 8 r/w-0 r-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 txenm txabtm (1) txlarbm (1) txerrm (1) txreqm rtrenm txmpri<1:0> bit 7 bit 0 legend: c = writable bit, but only 0 can be written to clear the bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 see definition for bits 7-0, controls buffer n bit 7 txenm: tx/rx buffer selection bit 1 = buffer trbn is a transmit buffer 0 = buffer trbn is a receive buffer bit 6 txabtm: message aborted bit (1) 1 = message was aborted 0 = message completed transmission successfully bit 5 txlarbm: message lost arbitration bit (1) 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerrm: error detected during transmission bit (1) 1 = a bus error occurred while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreqm: message send request bit 1 = requests that a message be sent. the bit automa tically clears when the message is successfully sent 0 = clearing the bit to 0 while set requests a message abort bit 2 rtrenm: auto-remote transmit enable bit 1 = when a remote transmit is received, txreq will be set 0 = when a remote transmit is received, txreq will be unaffected bit 1-0 txmpri<1:0>: message transmission priority bits 11 = highest message priority 10 = high intermediate message priority 01 = low intermediate message priority 00 = lowest message priority note 1: this bit is cleared when the txreq bit is set. note: the buffers, sid, eid, dlc, data field and re ceive status registers are located in dma ram. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 251 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 19.6 ecan message buffers ecan message buffers are part of dma ram memory. they are not ecan special function registers. the user application must directly wr ite into the dma ram area that is configured for ecan message buffers. the location and size of the buffer area is defined by the user application. buffer 19-1: ecan? message buffer word 0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid5 sid4 sid3 sid2 sid1 sid0 srr ide bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-2 sid<10:0>: standard identifier bits bit 1 srr: substitute remote request bit 1 = message will request remote transmission 0 = normal message bit 0 ide: extended identifier bit 1 = message will transmit extended identifier 0 = message will transmit standard identifier buffer 19-2: ecan? message buffer word 1 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x e i d 1 7e i d 1 6e i d 1 5e i d 1 4 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid13 eid12 eid11 eid10 eid9 eid8 eid7 eid6 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-0 eid<17:6>: extended identifier bits downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 252 ? 2007-2012 microchip technology inc. ( buffer 19-3: ecan? message buffer word 2 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid5 eid4 eid3 eid2 eid1 eid0 rtr rb1 bit 15 bit 8 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x rb0 dlc3 dlc2 dlc1 dlc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-10 eid<5:0>: extended identifier bits bit 9 rtr: remote transmission request bit 1 = message will request remote transmission 0 = normal message bit 8 rb1: reserved bit 1 user must set this bit to 0 per can protocol. bit 7-5 unimplemented: read as 0 bit 4 rb0: reserved bit 0 user must set this bit to 0 per can protocol. bit 3-0 dlc<3:0>: data length code bits buffer 19-4: ecan ? message buffer word 3 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 1 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 byte 1<15:8>: ecan? message byte 0 bit 7-0 byte 0<7:0>: ecan message byte 1 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 253 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 buffer 19-5: ecan ? message buffer word 4 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 3 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 byte 3<15:8>: ecan? message byte 3 bit 7-0 byte 2<7:0>: ecan message byte 2 buffer 19-6: ecan ? message buffer word 5 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 5 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 byte 5<15:8>: ecan? message byte 5 bit 7-0 byte 4<7:0>: ecan message byte 4 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 254 ? 2007-2012 microchip technology inc. buffer 19-7: ecan ? message buffer word 6 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 7 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x byte 6 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 byte 7<15:8>: ecan? message byte 7 bit 7-0 byte 6<7:0>: ecan message byte 6 buffer 19-8: ecan? message buffer word 7 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x filhit<4:0> (1) bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-8 filhit<4:0>: filter hit code bits (1) encodes number of filter that resulted in writing this buffer. bit 7-0 unimplemented: read as 0 note 1: these bits are only written by the module for receive buffers, and are unused for transmit buffers. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 255 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 20.0 data converter interface (dci) module 20.1 module introduction the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 data converter interface (dci) module allows simple interfacing of devices, such as audio coder/decoders (codecs), adc and d/a converters. the following interfaces are supported: framed synchronous serial transfer (single or multi-channel) inter-ic sound (i 2 s) interface ac-link compliant mode the dci module provides the following general features: programmable word size up to 16 bits supports up to 16 time slots, for a maximum frame size of 256 bits data buffering for up to 4 samples without cpu overhead figure 20-1: dci module block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 20. data converter interface (dci) (ds70288) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. bcg control bits 16-bit data bus sample rate generator sckd fsd dci buffer frame synchronization generator control unit dci shift register receive buffer registers w/shadow f osc /4 word size selection bits frame length selection bits dci mode selection bits csck cofs csdi csdo 15 0 transmit buffer registers w/shadow downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 256 ? 2007-2012 microchip technology inc. 20.2 dci resources many useful resources related to dci are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 20.2.1 key resources section 20. data converter interface (dci) (ds70288) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 257 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 20.3 dci control registers register 20-1: dcicon1: dci control register 1 r/w-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 dcien d c i s i d l dloop csckd cscke cofsd bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 unfm csdom djst c o f s m < 1 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 dcien: dci module enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as 0 bit 13 dcisidl: dci stop in idle control bit 1 = module will halt in cpu idle mode 0 = module will continue to operate in cpu idle mode bit 12 unimplemented: read as 0 bit 11 dloop: digital loopback mode control bit 1 = digital loopback mode is enabled. csdi and csdo pins internally connected. 0 = digital loopback mode is disabled bit 10 csckd: sample clock direction control bit 1 = csck pin is an input when dci module is enabled 0 = csck pin is an output when dci module is enabled bit 9 cscke: sample clock edge control bit 1 = data changes on serial clock falling edge, sampled on serial clock rising edge 0 = data changes on serial clock rising edge, sampled on serial clock falling edge bit 8 cofsd: frame synchronization direction control bit 1 = cofs pin is an input when dci module is enabled 0 = cofs pin is an output when dci module is enabled bit 7 unfm: underflow mode bit 1 = transmit last value written to the tr ansmit registers on a transmit underflow 0 = transmit 0 s on a transmit underflow bit 6 csdom: serial data output mode bit 1 = csdo pin will be tri-stated during disabled transmit time slots 0 = csdo pin drives 0 s during disabled transmit time slots bit 5 djst: dci data justification control bit 1 = data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse 0 = data transmission/reception is begun one serial clock cycle after frame synchronization pulse bit 4-2 unimplemented: read as 0 bit 1-0 cofsm<1:0>: frame sync mode bits 11 = 20-bit ac-link mode 10 = 16-bit ac-link mode 01 = i 2 s frame sync mode 00 = multi-channel frame sync mode downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 258 ? 2007-2012 microchip technology inc. register 20-2: dcicon2: dci control register 2 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 blen<1:0> c o f s g 3 bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cofsg<2:0> ws<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-10 blen<1:0>: buffer length control bits 11 = four data words will be buffered between interrupts 10 = three data words will be buffered between interrupts 01 = two data words will be buffered between interrupts 00 = one data word will be buffered between interrupts bit 9 unimplemented: read as 0 bit 8-5 cofsg<3:0>: frame sync generator control bits 1111 = data frame has 16 words 0010 = data frame has 3 words 0001 = data frame has 2 words 0000 = data frame has 1 word bit 4 unimplemented: read as 0 bit 3-0 ws<3:0>: dci data word size bits 1111 = data word size is 16 bits 0100 = data word size is 5 bits 0011 = data word size is 4 bits 0010 = invalid selection . do not use. unexpected results may occur. 0001 = invalid selection . do not use. unexpected results may occur. 0000 = invalid selection . do not use. unexpected results may occur. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 259 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 20-3: dcicon3: dci control register 3 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 b c g < 1 1 : 8 > bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bcg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-0 bcg<11:0>: dci bit clock generator control bits downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 260 ? 2007-2012 microchip technology inc. register 20-4: dcistat: dci status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 slot<3:0> bit 15 bit 8 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 rov rful tunf tmpty bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-8 slot<3:0>: dci slot status bits 1111 = slot 15 is currently active 0010 = slot 2 is currently active 0001 = slot 1 is currently active 0000 = slot 0 is currently active bit 7-4 unimplemented: read as 0 bit 3 rov: receive overflow status bit 1 = a receive overflow has occurred for at least one receive register 0 = a receive overflow has not occurred bit 2 rful: receive buffer full status bit 1 = new data is available in the receive registers 0 = the receive registers have old data bit 1 tunf: transmit buffer underflow status bit 1 = a transmit underflow has occurred for at least one transmit register 0 = a transmit underflow has not occurred bit 0 tmpty: transmit buffer empty status bit 1 = the transmit registers are empty 0 = the transmit regi sters are not empty downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 261 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 20-5: rscon: dci re ceive slot control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rse15 rse14 rse13 rse12 rse11 rse10 rse9 rse8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rse7 rse6 rse5 rse4 rse3 rse2 rse1 rse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 rse<15:0>: receive slot enable bits 1 = csdi data is received during the individual time slot n 0 = csdi data is ignored during the individual time slot n register 20-6: tscon: dci tr ansmit slot control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tse15 tse14 tse13 tse12 tse11 tse10 tse9 tse8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tse7 tse6 tse5 tse4 tse3 tse2 tse1 tse0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 tse<15:0>: transmit slot enable control bits 1 = transmit buffer contents are sent during the individual time slot n 0 = csdo pin is tri-stated or driven to logic 0 , during the individual time slot, depending on the state of the csdom bit downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 262 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 263 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 21.0 10-bit/12-bit analog-to- digital con verter (adc) the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 devices have up to 13 adc input channels. the ad12b bit (ad1con1<10>) allows each of the adc modules to be configured by the user as either a 10-bit, 4-sample/hold adc ( default configuration) or a 12-bit, 1-sample/hold adc. 21.1 key features the 10-bit adc configuration has the following key features: successive approximation (sar) conversion conversion speeds of up to 1.1 msps up to 13 analog input pins external voltage reference input pins simultaneous sampling of up to four analog input pins automatic channel scan mode selectable conversion trigger source selectable buffer fill modes four result alignment options (signed/unsigned, fractional/integer) operation during cpu sleep and idle modes the 12-bit adc configuration supports all the above features, except: in the 12-bit configurati on, conversion speeds of up to 500 ksps are supported there is only one sample/hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported depending on the particular device pinout, the adc can have up to 13 analog input pins, designated an0 through an12. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs can be shared with other ana- log input pins. the actual number of analog input pins and external voltage reference input configuration depends on the specific device. block diagrams of the adc module are shown in figure 21-1 and figure 21-2 . 21.2 adc initialization the following configuration steps should be performed. 1. configure the adc module: a) select port pins as analog inputs (ad1pcfgh<15:0> or ad1pcfgl<15:0>) b) select voltage reference source to match expected range on analog inputs (ad1con2<15:13>) c) select the analog conversion clock to match desired data rate with processor clock (ad1con3<7:0>) d) determine how many s/h channels are used (ad1con2<9:8> and ad1pcfgh<15:0> or ad1pcfgl<15:0>) e) select the appropriate sample/conversion sequence (ad1con1<7:5> and ad1con3<12:8>) f) select how conversion results are presented in the buffer (ad1con1<9:8>) g) turn on adc module (ad1con1<15>) 2. configure adc interrupt (if required): a) clear the ad1if bit b) select adc interrupt priority 21.3 adc and dma if more than one conversion result needs to be buffered before triggering an interrupt, dma data transfers can be used. adc1 can trigger a dma data transfer. if adc1 is selected as the dma irq source, a dma transfer occurs when the ad1if bit gets set as a result of an adc1 sample conversion sequence. the smpi<3:0> bits (ad1con2<5:2>) are used to select how often the dma ram buffer pointer is incremented. the addmabm bit (ad1con1<12>) determines how the conversion results are filled in the dma ram buffer area being used for adc. if this bit is set, dma buffers are written in the order of conversion. the module provides an address to the dma channel that is the same as the address used for the non-dma stand- alone buffer. if the addmabm bit is cleared, then dma buffers are written in sca tter/gather mode. the module provides a scatter/gather address to the dma channel, based on the index of the analog input and the size of the dma buffer. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 16. analog-to-digital converter (adc) (ds70183) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: the adc module needs to be disabled before modifying the ad12b bit. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 264 ? 2007-2012 microchip technology inc. figure 21-1: adc1 module block diagram for dspic33fj32gp304, dspic33fj64gp204/804 and dspi c33fj128gp204/804 devices s/h0 s/h1 adc1buf0 an0 an12 an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa an9 v refl ch123sb ch123na ch123nb an6 + - s/h2 an1 an4 ch123sa an10 v refl ch123sb ch123na ch123nb an7 + - s/h3 an2 an5 ch123sa an11 v refl ch123sb ch123na ch123nb an8 + - ch1 (2) ch0 ch2 (2) ch3 (2) ch0sa<4:0> channel scan cscna alternate note 1: v ref +, v ref - inputs can be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. input selection vcfg<2:0> av dd av ss v ref - (1) v ref + (1) sar adc v refh v refl downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 265 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 21-2: adc1 module block diagram for dspic33fj32gp302, dspic33fj64gp202/802 and dspic3 3fj128gp202/802 devices s/h0 s/h1 an0 an12 an1 v refl ch0sb<4:0> ch0na ch0nb + - an0 an3 ch123sa an9 v refl ch123sb ch123na ch123nb + - s/h2 an1 an4 ch123sa an10 v refl ch123sb ch123na ch123nb + - s/h3 an2 an5 ch123sa an11 v refl ch123sb ch123na ch123nb + - ch1 (2) ch0 ch2 (2) ch3 (2) ch0sa<4:0> channel scan cscna alternate note 1: v ref +, v ref - inputs can be multiplexed with other analog inputs. 2: channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. input selection adc1buf0 vcfg<2:0> av dd av ss v ref - (1) v ref + (1) v refh v refl sar adc downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 266 ? 2007-2012 microchip technology inc. figure 21-3: adc conversion clock period block diagram 10 adc internal rc clock (2) t osc (1) x 2 adc conversion clock multiplier 1, 2, 3, 4, 5,..., 64 ad1con3<15> t cy t ad 6 ad1con3<5:0> note 1: refer to figure 9-2 for the derivation of fosc when the pll is enabled. if the pll is not used, fosc is equal to the clock source frequency. tosc = 1/fosc. 2: see the adc electrical characterist ics for the exact rc clock value. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 267 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 21.4 adc helpful tips 1. the smpi<3:0> (ad1con2 <5:2>) control bits: a) determine when the adc interrupt flag is set and an interrupt is generated if enabled. b) when the cscna bit (ad1con2<10>) is set to 1 , determines when the adc analog scan channel list defined in the ad1cssl/ ad1cssh registers starts over from the beginning. c) on devices without a dma peripheral, determines when adc result buffer pointer to adc1buf0-adc1buff, gets reset back to the beginning at adc1buf0. 2. on devices without a dma module, the adc has 16 result buffers. adc conversion results are stored sequentially in adc1buf0-adc1buff regardless of which analog inputs are being used subject to the smpi<3:0> bits (ad1con2<5:2>) and the condition described in 1c above. there is no relationship between the anx input being measured and which adc buffer (adc1buf0-adc1buff) that the conversion results will be placed in. 3. on devices with a dma module, the adc mod- ule has only 1 adc result buffer, (i.e., adc1buf0), per adc peripheral and the adc conversion result must be read either by the cpu or dma controller before the next adc conversion is complete to avoid overwriting the previous value. 4. the done bit (ad1con1<0>) is only cleared at the start of each conversion and is set at the completion of the conversion, but remains set indefinitely even through the next sample phase until the next conversion begins. if application code is monitoring the done bit in any kind of software loop, the user must consider this behavior because the cpu code execution is faster than the adc. as a result, in manual sam- ple mode, particularly where the users code is setting the samp bit (ad1con1<1>), the done bit should also be cleared by the user application just before setting the samp bit. 5. on devices with two adc modules, the adcxpcfg registers for both adc modules must be set to a logic 1 to configure a target i/o pin as a digital i/o pin. failure to do so means that any alternate digital input function will always see only a logic 0 as the digital input buffer is held in disable mode. 21.5 adc resources many useful resources related to adc are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 21.5.1 key resources section 16. analog-to-digital converter (adc) (ds70183) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using the link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 268 ? 2007-2012 microchip technology inc. 21.6 adc control registers register 21-1: ad1con1: adc1 control register 1 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 adon a d s i d l a d d m a b m ad12b form<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 hc,hs r/c-0 hc, hs ssrc<2:0> simsam asam samp done bit 7 bit 0 legend: hc = cleared by hardware hs = set by hardware c = clear only bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adon: adc operating mode bit 1 = adc module is operating 0 = adc is off bit 14 unimplemented: read as 0 bit 13 adsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 addmabm: dma buffer build mode bit 1 = dma buffers are written in the order of conversion. the module provides an address to the dma channel that is the same as the address used for the non-dma stand-alone buffer 0 = dma buffers are written in scatter/gather mode. the module provides a scatter/gather address to the dma channel, based on the index of t he analog input and the size of the dma buffer bit 11 unimplemented: read as 0 bit 10 ad12b: 10-bit or 12-bit operation mode bit 1 = 12-bit, 1-channel adc operation 0 = 10-bit, 4-channel adc operation bit 9-8 form<1:0>: data output format bits for 10-bit operation: 11 = signed fractional (d out = sddd dddd dd00 0000 , where s =.not.d<9>) 10 = fractional (d out = dddd dddd dd00 0000 ) 01 = signed integer (d out = ssss sssd dddd dddd , where s = .not.d<9>) 00 = integer (d out = 0000 00dd dddd dddd ) for 12-bit operation: 11 = signed fractional (d out = sddd dddd dddd 0000 , where s = .not.d<11>) 10 = fractional (d out = dddd dddd dddd 0000 ) 01 = signed integer (d out = ssss sddd dddd dddd , where s = .not.d<11>) 00 = integer (d out = 0000 dddd dddd dddd ) bit 7-5 ssrc<2:0>: sample clock source select bits 111 = internal counter ends sampling a nd starts conversion (auto-convert) 110 = reserved 101 = reserved 100 = gp timer (timer5 for adc1) compare ends sampling and starts conversion 011 = reserved 010 = gp timer (timer3 for adc1) compare ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing sample bit ends sampling and starts conversion bit 4 unimplemented: read as 0 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 269 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 3 simsam: simultaneous sample select bit (only applicable when chps<1:0> = 01 or 1x ) when ad12b = 1 , simsam is: u-0, unimplemented, read as 0 1 = samples ch0, ch1, ch2, ch3 simultaneously (when chps<1:0> = 1x ); or samples ch0 and ch1 simultaneously (when chps<1:0> = 01 ) 0 = samples multiple channels individually in sequence bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conversion. samp bit is auto-set 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit 1 = adc sample/hold amplifiers are sampling 0 = adc sample/hold amplifiers are holding if asam = 0 , software can write 1 to begin sampling. automatically set by hardware if asam = 1 . if ssrc = 000 , software can write 0 to end sampling and start conversion. if ssrc 000 , automatically cleared by hardware to end sampling and start conversion. bit 0 done: adc conversion status bit 1 = adc conversion cycle is completed. 0 = adc conversion not started or in progress automatically set by hardware when adc conversion is complete. software can write 0 to clear done status (software not allowed to write 1 ). clearing this bit does not affect any operation in progress. automatically cleared by hard ware at start of a new conversion. register 21-1: ad1con1: adc1 co ntrol register 1 (continued) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 270 ? 2007-2012 microchip technology inc. register 21-2: ad1con2: adc1 control register 2 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 vcfg<2:0> cscna chps<1:0> bit 15 bit 8 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs smpi<3:0> bufm alts bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 vcfg<2:0>: converter voltage reference configuration bits bit 12-11 unimplemented: read as 0 bit 10 cscna: scan input selections for ch0+ during sample a bit 1 = scan inputs 0 = do not scan inputs bit 9-8 chps<1:0>: selects channels utilized bits when ad12b = 1 , chps<1:0> is: u-0, unimplemented, read as 0 1x = converts ch0, ch1, ch2 and ch3 01 = converts ch0 and ch1 00 = converts ch0 bit 7 bufs: buffer fill status bit (only valid when bufm = 1 ) 1 = adc is currently filling buffer 0x8-0xf, user should access data in 0x0-0x7 0 = adc is currently filling buffer 0x0-0x7, user should access data in 0x8-0xf bit 6 unimplemented: read as 0 bit 5-2 smpi<3:0>: selects increment rate for dma addresse s bits or number of sample/conversion operations per interrupt 1111 = increments the dma address or generates interrupt after completion of every 16th sample/ conversion operation 1110 = increments the dma address or generates interrupt after completion of every 15th sample/ conversion operation 0001 = increments the dma address after completi on of every 2nd sample/conversion operation 0000 = increments the dma address after comp letion of every sample/conversion operation bit 1 bufm: buffer fill mode select bit 1 = starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt 0 = always starts filling buffer at address 0x0 bit 0 alts: alternate input sample mode select bit 1 = uses channel input selects for sample a on first sample and sample b on next sample 0 = always uses channel i nput selects for sample a adref+ adref- 000 a vdd a vss 001 external v ref +a vss 010 a vdd external v ref - 011 external v ref + external v ref - 1xx a vdd avss downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 271 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 21-3: ad1con3: adc1 control register 3 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc samc<4:0> (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcs<7:0> (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 adrc: adc conversion clock source bit 1 = adc internal rc clock 0 = clock derived from system clock bit 14-13 unimplemented: read as 0 bit 12-8 samc<4:0>: auto sample time bits (1) 11111 = 31 t ad 00001 = 1 t ad 00000 = 0 t ad bit 7-0 adcs<7:0>: adc conversion clock select bits (2) 11111111 = reserved 01000000 = reserved 00111111 = t cy (adcs<7:0> + 1) = 64 t cy = t ad 00000010 = t cy (adcs<7:0> + 1) = 3 t cy = t ad 00000001 = t cy (adcs<7:0> + 1) = 2 t cy = t ad 00000000 = t cy (adcs<7:0> + 1) = 1 t cy = t ad note 1: this bit only used if ad1con1<7:5> (ssrc<2:0>) = 111 . 2: this bit is not used if ad1con3<15> (adrc) = 1 . downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 272 ? 2007-2012 microchip technology inc. register 21-4: ad1con4: adc1 control register 4 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 dmabl<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-3 unimplemented: read as 0 bit 2-0 dmabl<2:0>: selects number of dma buffer locations per analog input bits 111 = allocates 128 words of buffer to each analog input 110 = allocates 64 words of buffer to each analog input 101 = allocates 32 words of buffer to each analog input 100 = allocates 16 words of buffer to each analog input 011 = allocates 8 words of buffer to each analog input 010 = allocates 4 words of buffer to each analog input 001 = allocates 2 words of buffer to each analog input 000 = allocates 1 word of buffer to each analog input downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 273 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 21-5: ad1chs123: adc1 in put channel 1, 2, 3 select register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ch123nb<1:0> ch123sb bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ch123na<1:0> ch123sa bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-9 ch123nb<1:0>: channel 1, 2, 3 negative i nput select for sample b bits when ad12b = 1 , chxnb is: u-0, unimplemented, read as 0 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 (1) 0x = ch1, ch2, ch3 negative input is v ref - bit 8 ch123sb: channel 1, 2, 3 positive input select for sample b bit when ad12b = 1 , chxsa is: u-0, unimplemented, read as 0 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 bit 7-3 unimplemented: read as 0 bit 2-1 ch123na<1:0>: channel 1, 2, 3 negative i nput select for sample a bits when ad12b = 1 , chxna is: u-0, unimplemented, read as 0 11 = ch1 negative input is an9, ch2 negative input is an10, ch3 negative input is an11 10 = ch1 negative input is an6, ch2 negative input is an7, ch3 negative input is an8 (1) 0x = ch1, ch2, ch3 negative input is v ref - bit 0 ch123sa: channel 1, 2, 3 positive input select for sample a bit when ad12b = 1 , chxsa is: u-0, unimplemented, read as 0 1 = ch1 positive input is an3, ch2 positive input is an4, ch3 positive input is an5 0 = ch1 positive input is an0, ch2 positive input is an1, ch3 positive input is an2 note 1: this bit setting is reserved in dspic33fj 128gpx02, dspic33fj64g px02 and dspic33fjgpx02 (28-pin) devices. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 274 ? 2007-2012 microchip technology inc. register 21-6: ad1chs0: adc1 input channel 0 select register r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ch0sb<4:0> bit 15 bit 8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ch0sa<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ch0nb: channel 0 negative input select for sample b bit same definition as bit 7. bit 14-13 unimplemented: read as 0 bit 12-8 ch0sb<4:0>: channel 0 positive input select for sample b bits 01100 = channel 0 positive input is an12 01011 = channel 0 positive input is an11 01000 = channel 0 positive input is an8 (1) 00111 = channel 0 positive input is an7 (1) 00110 = channel 0 positive input is an6 (1) 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 7 ch0na: channel 0 negative input select for sample a bit 1 = channel 0 negative input is an1 0 = channel 0 negative input is v ref - bit 6-5 unimplemented: read as 0 bit 4-0 ch0sa<4:0>: channel 0 positive input select for sample a bits 01100 = channel 0 positive input is an12 01011 = channel 0 positive input is an11 01000 = channel 0 positive input is an8 (1) 00111 = channel 0 positive input is an7 (1) 00110 = channel 0 positive input is an6 (1) 00010 = channel 0 positive input is an2 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 note 1: these bit settings are reserved on dspic33fj1 28gpx02, dspic33fj64gpx0 2 and dspic33fj32gpx02 (28-pin) devices. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 275 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 21-7: ad1cssl: adc1 in put scan select register low (1,2) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css12 css11 css10 css9 css8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 css7 css6 css5 css4 css3 css2 css1 css0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-12 unimplemented: read as 0 bit 11-0 css<11:0>: adc input scan selection bits 1 = select anx for input scan 0 = skip anx for input scan note 1: on devices without 13 analog inputs, all ad1cssl bits can be selected by the user application. however, inputs selected for scan without a corresponding input on device converts v refl . 2: cssx = anx, where x = 0 through 12. register 21-8: ad1pcfgl: adc1 po rt configuration register low (1,2,3) u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg12 pcfg11 pcfg10 pcfg9 pcfg8 bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12-0 pcfg<12:0>: adc port configuration control bits 1 = port pin in digital mode, port read input enabled, adc input multiplexer connected to av ss 0 = port pin in analog mode, port read input disabled, adc samples pin voltage note 1: on devices without 13 analog inputs, all pcfg bits ar e r/w by user software. however, the pcfg bits are ignored on ports without a corresponding input on device. 2: pcfgx = anx, where x = 0 through 12. 3: pcfgx bits have no effect if adc module is disabled by setting adxmd bit in the pmdx register. in this case all port pins multiplexed with anx will be in digital mode. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 276 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 277 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 22.0 audio digital-to-analog converter (dac) the audio digital-to-analog converter (dac) module is a 16-bit delta-sigma signal converter designed for audio applications. it has two output channels, left and right to support stereo applications. each dac output channel provides three volt age outputs, positive dac output, negative dac output, and the midpoint voltage output for the dspic33fj64gp804 and dspic33fj128gp804 devices. the dspic33fj64gp802 a nd dspic33fj128gp802 devices provide positive dac output and negative dac output voltages. 22.1 key features 16-bit resolution (14-bit accuracy) second-order digital delta-sigma modulator 256 x over-sampling ratio 128-tap fir current-steering analog recon- struction filter 100 ksps maximum sampling rate user controllable sample clock input frequency 45 khz max differential analog outputs signal-to-noise: 90 db 4-deep input buffer 16-bit processor i/o, and dma interfaces 22.2 dac module operation the functional block diagram of the audio dac module is shown in figure 22-1 . the audio dac module provides a 4-deep data input fifo buffer for each output channel. if the dma module and/or the processor cannot provide output data in a timely manner, and the fifo becomes empty, the dac accepts data from the dac default data register (dacdflt). this safety feature is useful for industrial control applications where the dac output controls an important processor or machinery. the dacdflt register should be initialized with a safe output value. often the safe output value is either the midpoint value (0x8000) or a zero value (0x0000). the digital interpolator up-samples the input signals, where the over-sampling ratio is 256x which creates data points between the user supplied data points. the interpolator also includes processing by digital filters to provide noise shaping to move the converter noise above 20 khz (upper limit of the pass band). the output of the interpolator drives the sigma- delta modulator. the serial data bit stream from the sigma-delta modulator is processed by the reconstruction filter. the differential outputs of the reconstruction filter are amplified by op amps to provide the required peak-to-peak voltage swing. 22.3 dac output format the dac output data stream can be in a twos comple- ment signed number format or as an unsigned number format. the audio dac module feat ures the ability to accept the 16-bit input data in a twos complement signed number format or as an unsigned number format. the data formatting is controlled by the data format control bit (form<8>) in the dac1con register. the supported formats are: 1 = signed (twos complement) 0 = unsigned if the form bit is configured for unsigned data then the user input data yields the following behavior: 0xffff = most posi tive output voltage 0x8000 = mid point output voltage 0x7fff = a value just below the midpoint 0x0000 = minimum output voltage if the form bit is configured for signed data then the user input data yields the following behavior: 0x7fff = most positive output voltage 0x0000 = mid point output voltage 0xffff = value just below the midpoint 0x8000 = minimum output voltage the audio dac provides an analog output proportional to the digital input value. the maximum 100,000 samples per second (100 ksps) update rate provides good quality audio reproduction. note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 33. audio digital-to- analog converter (dac) (ds70211) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: the dac module is designed specifically for audio applications and is not recommended for control type applications. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 278 ? 2007-2012 microchip technology inc. 22.4 dac clock the dac clock signal clocks the internal logic of the audio dac module. the data sample rate of the audio dac is an integer division of the rate of the dac clock. the dac clock is generated via a clock divider circuit that accepts an auxiliary clock from the auxiliary oscillator. the divisor ratio is programmed by clock divider bits (dacfdiv<6:0>) in the dac control register (dac1con). the resulting dac clock must not exceed 25.6 mhz. if lower sample rates are to be used, then the dac filter clock frequency may be reduced to reduce power consumption. the dac clock frequency is 256 times the sampling frequency. figure 22-1: block diagram of audio digital-to-analog (dac) converter figure 22-2: audio dac output for ramp input (unsigned) dac1rdat dac1ldat d/a d/a control clk div dacdflt amp 16-bit data bus amp aclk note 1: if dac1rdat and dac1ldat are empty, data will be taken from the dacdflt register. note 1 note 1 dac1lmdac1lp dac1ln dac1rmdac1rp dac1rn right channel left channel dacfdiv<6:0> 0x0000 0xffff dac input count (dac1rdat) v dacm v dacm positive dac output (dac1rp) negative dac output (dac1rn) v dach v dacl v dacl v dach note: v od + = v dach C v dacl , v od - = v dacl C v dach ; refer to audio dac module specifications, table 30-46 , for typical values. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 279 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 22.5 dac resources many useful resources related to dac are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 22.5.1 key resources section 33. audio digital-to-analog converter (dac) (ds70211) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 280 ? 2007-2012 microchip technology inc. 22.6 dac control registers register 22-1: dac1con: dac control register r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 r/w-0 dacen dacsidl ampon f o r m bit 15 bit 8 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 d a c f d i v < 6 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 dacen: dac1 enable bit 1 = enables module 0 = disables module bit 14 unimplemented: read as 0 bit 13 dacsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 ampon: enable analog output amplifier in sleep mode/stop in idle mode bit 1 = analog output amplifier is enabled during sleep mode/stop in idle mode 0 = analog output amplifier is disabled during sleep mode/stop in idle mode bit 11-9 unimplemented: read as 0 bit 8 form: data format select bit 1 = signed integer 0 = unsigned integer bit 7 unimplemented: read as 0 bit 6-0 dacfdiv<6:0>: dac clock divider bit 1111111 = divide input clock by 128 0000101 = divide input clock by 6 (default) 0000010 = divide input clock by 3 0000001 = divide input clock by 2 0000000 = divide input clock by 1 (no divide) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 281 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 22-2: dac1stat: dac status register r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r-0 r-0 loen l m v o e n litype lfull lempty bit 15 bit 8 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r-0 r-0 roen r m v o e n ritype rfull rempty bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 loen: left channel dac output enable bit 1 = positive and negative dac outputs are enabled 0 = dac outputs are disabled bit 14 unimplemented: read as 0 bit 13 lmvoen: left channel midpoint dac output voltage enable bit 1 = midpoint dac output is enabled 0 = midpoint output is disabled bit 12-11 unimplemented: read as 0 bit 10 litype: left channel type of interrupt bit 1 = interrupt if fifo is empty 0 = interrupt if fifo is not full bit 9 lfull: status, left channel data input fifo is full bit 1 = fifo is full 0 = fifo is not full bit 8 lempty: status, left channel data input fifo is empty bit 1 = fifo is empty 0 = fifo is not empty bit 7 roen: right channel dac output enable bit 1 = positive and negative dac outputs are enabled 0 = dac outputs are disabled bit 6 unimplemented: read as 0 bit 5 rmvoen: right channel midpoint dac output voltage enable bit 1 = midpoint dac output is enabled 0 = midpoint output is disabled bit 4-3 unimplemented: read as 0 bit 2 ritype: right channel type of interrupt bit 1 = interrupt if fifo is empty 0 = interrupt if fifo is not full bit 1 rfull: status, right channel data input fifo is full bit 1 = fifo is full 0 = fifo is not full bit 0 rempty: status, right channel data input fifo is empty bit 1 = fifo is empty 0 = fifo is not empty downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 282 ? 2007-2012 microchip technology inc. register 22-3: dac1dflt: dac default data register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacdflt<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacdflt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 dacdflt<15:0>: dac default value bits register 22-4: dac1ldat: dac left data register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacldat<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacldat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 dacldat<15:0>: left channel data port bits register 22-5: dac1rdat: dac right data register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacrdat<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dacrdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-0 dacrdat<15:0>: right channel data port bits downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 283 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 23.0 comparator module the comparator module provides a set of dual input comparators. the inputs to the comparator can be con- figured to use any one of the four pin inputs (c1in+, c1in-, c2in+ and c2in-) as well as the comparator voltage reference input (cv ref ). figure 23-1: comparator i/o operating modes note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 34. comparator (ds70212) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. note: this peripheral cont ains output func- tions that may need to be configured by the peripheral pin se lect feature. for more information, see section 11.6 peripheral pin select . c2 c2in- v in - v in + c2in+ cv ref c2in+ c2out (1) c2out (cmcon<7>) c1 c1in- v in - v in + c1in+ cv ref c1in+ c1out (1) c1out (cmcon<6>) c1neg c1pos c2neg c2pos c1inv c2inv c1outen c2outen c1en c2en note 1: this peripherals outputs must be assigned to an available rpn pin before use. refer to section 11.6 peripheral pin select for more information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 284 ? 2007-2012 microchip technology inc. 23.1 comparator resources many useful resources related to comparators are provided on the main produ ct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 23.1.1 key resources section 34. comparator (ds70212) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 285 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 23.2 comparator control register register 23-1: cmcon: comparator control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cmidl c2evt c1evt c2en c1en c2outen (1) c1outen (2) bit 15 bit 8 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out c2inv c1inv c2neg c2pos c1neg c1pos bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 cmidl: stop in idle mode bit 1 = when device enters idle mode, module does not generate interrupts. module is still enabled. 0 = continue normal module operation in idle mode bit 14 unimplemented: read as 0 bit 13 c2evt: comparator 2 event bit 1 = comparator output changed states 0 = comparator output did not change states bit 12 c1evt: comparator 1 event bit 1 = comparator output changed states 0 = comparator output did not change states bit 11 c2en: comparator 2 enable bit 1 = comparator is enabled 0 = comparator is disabled bit 10 c1en: comparator 1 enable bit 1 = comparator is enabled 0 = comparator is disabled bit 9 c2outen: comparator 2 output enable bit (1) 1 = comparator output is driven on the output pad 0 = comparator output is not driven on the output pad bit 8 c1outen: comparator 1 output enable bit (2) 1 = comparator output is driven on the output pad 0 = comparator output is not driven on the output pad bit 7 c2out: comparator 2 output bit when c2inv = 0 : 1 =c2 v in + > c2 v in - 0 =c2 v in + < c2 v in - when c2inv = 1 : 0 =c2 v in + > c2 v in - 1 =c2 v in + < c2 v in - note 1: if c2outen = 1 , the c2out peripheral output must be configured to an available rpx pin. see section 11.6 peripheral pin select for more information. 2: if c1outen = 1 , the c1out peripheral output must be configured to an available rpx pin. see section 11.6 peripheral pin select for more information. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 286 ? 2007-2012 microchip technology inc. bit 6 c1out: comparator 1 output bit when c1inv = 0 : 1 =c1 v in + > c1 v in - 0 =c1 v in + < c1 v in - when c1inv = 1 : 0 =c1 v in + > c1 v in - 1 =c1 v in + < c1 v in - bit 5 c2inv: comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv: comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 c2neg: comparator 2 negative input configure bit 1 = input is connected to v in + 0 = input is connected to v in - see figure 23-1 for the comparator modes. bit 2 c2pos: comparator 2 positive input configure bit 1 = input is connected to v in + 0 = input is connected to cv ref see figure 23-1 for the comparator modes. bit 1 c1neg: comparator 1 negative input configure bit 1 = input is connected to v in + 0 = input is connected to v in - see figure 23-1 for the comparator modes. bit 0 c1pos: comparator 1 positive input configure bit 1 = input is connected to v in + 0 = input is connected to cv ref see figure 23-1 for the comparator modes. register 23-1: cmcon: comparator control register (continued) note 1: if c2outen = 1 , the c2out peripheral output must be c onfigured to an available rpx pin. see section 11.6 peripheral pin select for more information. 2: if c1outen = 1 , the c1out peripheral output must be c onfigured to an available rpx pin. see section 11.6 peripheral pin select for more information. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 287 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 23.3 comparator voltage reference 23.3.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register ( register 23-2 ). the comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref -. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output. figure 23-2: comparator voltage reference block diagram 16-to-1 mux 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 rr r r r r 16 steps cvrr cv ref cvr3cvr2 cvr1 cvr0 cvrcon<3:0> av ss cv rsrc cvroe (cvrcon<6>) cv refin downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 288 ? 2007-2012 microchip technology inc. register 23-2: cvrcon: comparator voltage reference control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w -0 r/w -0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr cvrss cvr<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7 cvren: comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe: comparator v ref output enable bit 1 =cv ref voltage level is output on cv ref pin 0 =cv ref voltage level is disconnected from cv ref pin bit 5 cvrr: comparator v ref range selection bit 1 =cv rsrc range should be 0 to 0.625 cv rsrc with cv rsrc /24 step size 0 =cv rsrc range should be 0.25 to 0.719 cv rsrc with cv rsrc /32 step size bit 4 cvrss: comparator v ref source selection bit 1 = comparator reference source cv rsrc = v ref + C v ref - 0 = comparator reference source cv rsrc = av dd C av ss bit 3-0 cvr<3:0>: comparator v ref value selection 0 cvr<3:0> 15 bits when cvrr = 1 : cv ref = (cvr <3:0 > / 24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc )+ (cvr <3:0>/32 ) ? (cv rsrc ) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 289 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 24.0 real-time clock and calendar (rtcc) this chapter discusses the real-time clock and calendar (rtcc) module, available on dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices, and its operation. the following are some of the key features of this module: time: hours, minutes, and seconds 24-hour format (military time) calendar: weekday, date, month and year alarm configurable year range: 2000 to 2099 leap year correction bcd format for compact firmware optimized for low-power operation user calibration with auto-adjust calibration range: 2.64 seconds error per month requirements: external 32.768 khz clock crystal alarm pulse or seconds clock output on rtcc pin the rtcc module is intended for applications where accurate time must be maintained for extended periods of time with minimum to no intervention from the cpu. the rtcc module is optimized for low-power usage to provide extended battery lifetime while keeping track of time. the rtcc module is a 100-year clock and calendar with automatic leap year detection. the range of the clock is from 00:00:00 (midnight) on january 1, 2000 to 23:59:59 on december 31, 2099. the hours are available in 24-hour (military time) format. the clock provides a granularity of one second with half-second visibility to the user. figure 24-1: rtcc block diagram note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 37. real-time clock and calendar (rtcc) (ds70301) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. rtcc prescalers rtcc timer comparator compare registers repeat counter with masks rtcc interrupt logic rcfgcal alcfgrpt alarm event 32.768 khz input from sosc oscillator 0.5s rtcc clock domain alarm pulse rtcc interrupt cpu clock domain rtcval alrmval rtcc pin rtcoe downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 290 ? 2007-2012 microchip technology inc. 24.1 rtcc module registers the rtcc module registers are organized into three categories: rtcc control registers rtcc value registers alarm value registers 24.1.1 register mapping to limit the register inte rface, the rtcc timer and alarm time registers are accessed through corre- sponding register pointers. the rtcc value register window (rtcvalh and rtcvall) uses the rtcptr bits (rcfgcal<9:8>) to select the desired timer register pair (see table 24-1 ). by writing the rtcvalh byte, the rtcc pointer value, rtcptr<1:0> bits, decrement by one until they reach 00 . once they reach 00 , the minutes and seconds value will be accessible through rtcvalh and rtcvall until the pointer value is manually changed. table 24-1: rtcval register mapping the alarm value register window (alrmvalh and alrmvall) uses the alrmptr bits (alcfgrpt<9:8>) to select the desired alarm register pair (see table 24-2 ). by writing the alrmvalh byte, the alarm pointer value, alrmptr<1:0> bits, decrement by one until they reach 00 . once they reach 00 , the alrmmin and alrmsec value will be accessible through alrmvalh and alrmvall until the pointer value is manually changed. table 24-2: alrmval register mapping considering that the 16-bit core does not distinguish between 8-bit and 16-bit re ad operations, the user must be aware that when readin g either the alrmvalh or alrmvall bytes will decrement the alrmptr<1:0> value. the same applies to the rtcvalh or rtcvall bytes with the rtcptr<1:0> being decremented. 24.1.2 write lock in order to perform a write to any of the rtcc timer registers, the rtcwren bit (rcfgcal<13>) must be set (refer to example 24-1 ). example 24-1: setting the rtcwren bit rtcptr <1:0> rtcc value register window rtcval<15:8> rtcval<7:0> 00 minutes seconds 01 weekday hours 10 month day 11 year alrmptr <1:0> alarm value register window alrmval<15:8> alrmval<7:0> 00 alrmmin alrmsec 01 alrmwd alrmhr 10 alrmmnth alrmday 11 note: this only applies to read operations and not write operations. note: to avoid accidental writes to the timer, it is recommended that the rtcwren bit (rcfgcal<13>) is kept clear at any other time. for the rtcwren bit to be set, there is only 1 instruction cycle time window allowed between the 55h/aa sequence and the setting of rtcwren; therefore, it is re commended that code follow the procedure in example 24-1 . mov #nvmkey, w1 ;move the address of nvmkey into w1 mov #0x55, w2 mov #0xaa, w3 mov w2, [w1] ;start 55/aa sequence mov w3, [w1] bset rcfgcal, #13 ;set the rtcwren bit downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 291 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 24.2 rtcc resources many useful resources related to rtcc are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 24.2.1 key resources section 37. real-time clock and calendar (rtcc) (ds70301) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 292 ? 2007-2012 microchip technology inc. 24.3 rtcc registers register 24-1: rcfgcal: rtcc calibration and configuration register (1) r/w-0 u-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 rtcen (2) rtcwren rtcsync halfsec (3) rtcoe rtcptr<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 rtcen: rtcc enable bit (2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as 0 bit 13 rtcwren: rtcc value registers write enable bit 1 = rtcvalh and rtcvall register s can be written to by the user 0 = rtcvalh and rtcvall registers are locked out from being written to by the user bit 12 rtcsync: rtcc value registers read synchronization bit 1 = rtcvalh, rtcvall and alcfgrpt registers can change while reading due to a rollover ripple resulting in an invalid data read. if the register is read twice and results in the same data, the data can be assumed to be valid. 0 = rtcvalh, rtcvall or alcfgrpt registers c an be read without concern over a rollover ripple bit 11 halfsec: half-second status bit (3) 1 = second half period of a second 0 = first half period of a second bit 10 rtcoe: rtcc output enable bit 1 = rtcc output enabled 0 = rtcc output disabled bit 9-8 rtcptr<1:0>: rtcc value register window pointer bits points to the corresponding rtcc value regist ers when reading rtcvalh and rtcvall registers; the rtcptr<1:0> value decrements on every re ad or write of rtcvalh until it reaches 00 . rtcval<15:8>: 00 = minutes 01 = weekday 10 = month 11 = reserved rtcval<7:0>: 00 = seconds 01 = hours 10 = day 11 = year note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to 0 on a write to the lower half of the minsec register. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 293 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 bit 7-0 cal<7:0>: rtc drift calibration bits 11111111 = minimum negative adjustment; subtracts 4 rtc clock pulses every one minute 10000000 = maximum negative adjustment; subtracts 512 rtc clock pulses every one minute 01111111 = maximum positive adjustment; adds 508 rtc clock pulses every one minute 00000001 = minimum positive adjustment; adds 4 rtc clock pulses every one minute 00000000 = no adjustment register 24-1: rcfgcal: rtcc calibration and configuration register (1) (continued) note 1: the rcfgcal register is only affected by a por. 2: a write to the rtcen bit is only allowed when rtcwren = 1 . 3: this bit is read-only. it is cleared to 0 on a write to the lower half of the minsec register. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 294 ? 2007-2012 microchip technology inc. register 24-2: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as 0 bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe bit (rcfgcal<10>) needs to be set. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 295 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 24-3: alcfgrpt: alarm configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen chime amask<3: 0> alrmptr<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 alrmen: alarm enable bit 1 = alarm is enabled (cleared automatically after an alarm event whenever arpt<7:0> = 0x00 and chime = 0 ) 0 = alarm is disabled bit 14 chime: chime enable bit 1 = chime is enabled; arpt<7:0> bits are allowed to roll over from 0x00 to 0xff 0 = chime is disabled; arpt<7:0> bits stop once they reach 0x00 bit 13-10 amask<3:0>: alarm mask configuration bits 11xx = reserved C do not use 101x = reserved C do not use 1001 = once a year (except when configured for february 29th, once every 4 years) 1000 = once a month 0111 = once a week 0110 = once a day 0101 = every hour 0100 = every 10 minutes 0011 = every minute 0010 = every 10 seconds 0001 = every second 0000 = every half second bit 9-8 alrmptr<1:0>: alarm value register window pointer bits points to the corresponding alarm value register s when reading alrmvalh and alrmvall registers; the alrmptr<1:0> value decrem ents on every read or write of alrmvalh until it reaches 00 . alrmval<15:8> : 11 = unimplemented 10 = alrmmnth 01 = alrmwd 00 = alrmmin alrmval<7:0> : 11 = unimplemented 10 = alrmday 01 = alrmhr 00 = alrmsec bit 7-0 arpt<7:0>: alarm repeat counter value bits 11111111 = alarm will repeat 255 more times 00000000 = alarm will not repeat the counter decrements on any alarm event. the co unter is prevented from ro lling over from 0x00 to 0xff unless chime = 1 . downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 296 ? 2007-2012 microchip technology inc. register 24-4: rtcval (when rtcptr<1:0> = 11 ): year value register (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x yrten<3:0> yrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-8 unimplemented: read as 0 bit 7-4 yrten<3:0>: binary coded decimal value of years tens digit; contains a value from 0 to 9 bit 3-0 yrone<3:0>: binary coded decimal value of years ones digit; contains a value from 0 to 9 note 1: a write to the year register is only allowed when rtcwren = 1 . register 24-5: rtcval (when rtcptr<1:0> = 10 ): month and day value register (1) u-0 u-0 u-0 r-x r-x r-x r-x r-x mthten0 mthone<3:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x dayten<1:0> dayone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 mthten0: binary coded decimal value of months tens digit; contains a value of 0 or 1 bit 11-8 mthone<3:0>: binary coded decimal value of months ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as 0 bit 5-4 dayten<1:0>: binary coded decimal value of days tens digit; contains a value from 0 to 3 bit 3-0 dayone<3:0>: binary coded decimal value of days ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 297 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 24-6: rtcval (when rtcptr<1:0> = 01 ): wkdyhr: weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x wday<2:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hrten<1:0> hrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 wday<2:0>: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as 0 bit 5-4 hrten<1:0>: binary coded decimal value of hours tens digit; contains a value from 0 to 2 bit 3-0 hrone<3:0>: binary coded decimal value of hours ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 24-7: rtcval (when rtcptr<1:0> = 00 ): minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x minten<2:0> minone<3:0> bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x secten<2:0> secone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 minten<2:0>: binary coded decimal value of minutes tens digit; contains a value from 0 to 5 bit 11-8 minone<3:0>: binary coded decimal value of minutes ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as 0 bit 6-4 secten<2:0>: binary coded decimal value of seconds tens digit; contains a value from 0 to 5 bit 3-0 secone<3:0>: binary coded decimal value of seconds ones digit; contains a value from 0 to 9 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 298 ? 2007-2012 microchip technology inc. register 24-8: alrmval (when alrmptr<1:0> = 10 ): alarm month and day value register (1) u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x mthten0 mthone<3:0> bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x dayten<1:0> dayone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-13 unimplemented: read as 0 bit 12 mthten0: binary coded decimal value of months tens digit; contains a value of 0 or 1 bit 11-8 mthone<3:0>: binary coded decimal value of months ones digit; contains a value from 0 to 9 bit 7-6 unimplemented: read as 0 bit 5-4 dayten<1:0>: binary coded decimal value of days tens digit; contains a value from 0 to 3 bit 3-0 dayone<3:0>: binary coded decimal value of days ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . register 24-9: alrmval (when alrmptr<1:0> = 01 ): alarm weekday and hours value register (1) u-0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x wday2 wday1 wday0 bit 15 bit 8 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hrten<1:0> hrone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-11 unimplemented: read as 0 bit 10-8 wday<2:0>: binary coded decimal value of weekday digit; contains a value from 0 to 6 bit 7-6 unimplemented: read as 0 bit 5-4 hrten<1:0>: binary coded decimal value of hours tens digit; contains a value from 0 to 2 bit 3-0 hrone<3:0>: binary coded decimal value of hours ones digit; contains a value from 0 to 9 note 1: a write to this register is only allowed when rtcwren = 1 . downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 299 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 24-10: alrmval (when alrmptr<1:0> = 00 ): alarm minutes and seconds value register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x minten<2:0> minone<3:0> bit 15 bit 8 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x secten<2:0> secone<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14-12 minten<2:0>: binary coded decimal value of minutes tens digit; contains a value from 0 to 5 bit 11-8 minone<3:0>: binary coded decimal value of minutes ones digit; contains a value from 0 to 9 bit 7 unimplemented: read as 0 bit 6-4 secten<2:0>: binary coded decimal value of seconds tens digit; contains a value from 0 to 5 bit 3-0 secone<3:0>: binary coded decimal value of seconds ones digit; contains a value from 0 to 9 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 300 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 301 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 25.0 programmable cyclic redundancy check (crc) generator the programmable crc generator offers the following features: user-programmable polynomial crc equation interrupt output data fifo 25.1 overview the module implements a software configurable crc generator. the terms of the polynomial and its length can be programmed using the crcxor bits (x<15:1>) and the crccon bits (plen<3:0>), respectively. equation 25-1: crc equation to program this polynomial into the crc generator, the crc register bits should be set as shown in table 25-1 . table 25-1: example crc setup for the value of x<15:1>, the 12th bit and the 5th bit are set to 1 , as required by the crc equation. the 0th bit required by the crc equation is always xored. for a 16-bit polynomial, the 16th bit is also always assumed to be xored; therefore, the x<15:1> bits do not have the 0th bit or the 16th bit. the topology of a standard crc generator is shown in figure 25-2 . figure 25-1: crc shifter details note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 36. programmable cyclic redundancy check (crc) (ds70298) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 memory organization in this data sheet for de vice-specific register and bit information. bit name bit value plen<3:0> 1111 x<15:1> 000100000010000 x 16 x 12 x 5 1 +++ in out bit 0 01 p_clk x1 in out bit 1 01 p_clk x2 in out bit 2 01 p_clk x3 in out bit 15 01 p_clk x15 xor d out 01 2 1 5 plen<3:0> hold hold hold hold crc read bus crc write bus crc shift register downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 302 ? 2007-2012 microchip technology inc. figure 25-2: crc generator reconfigured for x 16 + x 12 + x 5 + 1 25.2 user interface 25.2.1 data interface to start serial shifting, a 1 must be written to the crcgo bit. the module incorporates a fifo that is 8 deep when plen (plen<3:0>) > 7, and 16 deep, otherwise. the data for which the crc is to be calculated must first be written into the fifo. the smallest data element that can be written into the fifo is one byte. for example, if plen = 5, then the size of the data is plen + 1 = 6. the data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = bxx once data is written into the crcwdat msb (as defined by plen), the value of vword (vword<4:0>) increments by one. the serial shifter starts shifting data into the crc engine when crcgo = 1 and vword > 0. when the msb is shifted out, vword decrements by one. the serial shifter continues shifting until the vword reaches 0. therefore, for a given value of plen, it will take (plen + 1) * vword number of clock cycles to complete the crc calculations. when vword reaches 8 (or 16), the crcful bit will be set. when vword reaches 0, the crcmpt bit will be set. to continually feed data into the crc engine, the rec- ommended mode of operation is to initially prime the fifo with a sufficient num ber of words so no interrupt is generated before the next word can be written. once that is done, start the crc by setting the crcgo bit to 1 . from that point onward, the vword<4:0> bits should be polled. if they re ad less than 8 or 16, another word can be written into the fifo. to empty words already written into a fifo, the crcgo bit must be set to 1 and the crc shifter allowed to run until the crcmpt bit is set. also, to get the correct crc reading, it will be necessary to wait for the crcmpt bit to go high before reading the crcwdat register. if a word is written when the crcful bit is set, the vword pointer will roll over to 0. the hardware will then behave as if the fifo is empty. however, the con- dition to generate an interrupt will not be met; therefore, no interrupt will be generated (see section 25.2.2 interrupt operation ). at least one instruction cycl e must pass after a write to crcwdat before a read of the vword bits is done. 25.2.2 interrupt operation when the vword<4:0> bits make a transition from a value of 1 to 0 , an interrupt will be generated. 25.3 operation in power-saving modes 25.3.1 sleep mode if sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 25.3.2 idle mode to continue full module operation in idle mode, the csidl bit must be cleared prior to entry into the mode. if csidl = 1 , the module will behave the same way as it does in sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. d q bit 0 p_clk dq bit 4 p_clk dq bit 5 p_clk dq bit 12 p_clk xor sdox crc read bus crc write bus dq bit 15 p_clk downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 303 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 25.4 programmable crc resources many useful resources related to programmable crc are provided on the main pr oduct page of the microchip web site for the devi ces listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 25.4.1 key resources section 36. programmable cyclic redundancy check (crc) (ds70298) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 304 ? 2007-2012 microchip technology inc. 25.5 programmable crc registers register 25-1: crccon: crc control register u-0 u-0 r/w-0 r-0 r-0 r-0 r-0 r-0 csidl vword<4:0> bit 15 bit 8 r-0 r-1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 crcful crcmpt crcgo plen<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as 0 bit 13 csidl: crc stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-8 vword<4:0>: pointer value bits indicates the number of valid words in the fifo. has a maximum value of 8 when plen<3:0> is greater than 7, or 16 when plen<3:0> is less than or equal to 7. bit 7 crcful: fifo full bit 1 = fifo is full 0 = fifo is not full bit 6 crcmpt: fifo empty bit 1 = fifo is empty 0 = fifo is not empty bit 5 unimplemented: read as 0 bit 4 crcgo: start crc bit 1 = start crc serial shifter 0 = turn off crc serial shifter after fifo is empty bit 3-0 plen<3:0>: polynomial length bits denotes the length of the polynomial to be generated minus 1. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 305 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 25-2: crcxor: crc xo r polynomial register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 x<15:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 x<7:1> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-1 x<15:1>: xor of polynomial term x n enable bits bit 0 unimplemented: read as 0 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 306 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 307 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 26.0 parallel master port (pmp) the parallel master port (pmp) module is a parallel 8-bit i/o module, specifically designed to communi- cate with a wide variety of parallel devices, such as communication peripherals , lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp is highly configurable. key features of the pmp module include: fully multiplexed address/data mode demultiplexed or partially multiplexed address/ data mode: - up to 11 address lines with single chip select - up to 12 address lines without chip select one chip select line programmable strobe options - individual read and write strobes or; - read/write strobe with enable strobe address auto-increment/auto-decrement programmable address/data multiplexing programmable polarity on control signals legacy parallel slave port support enhanced parallel slave support: - address support - 4-byte deep auto-incrementing buffer programmable wait states selectable input voltage levels figure 26-1: pmp module overview note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to section 35. parallel master port (pmp) (ds70299) of the dspic33f/pic24h family reference manual , which is available from the microchip website ( www.microchip.com ). 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. pma<0> pmbe pmrd pmwr pmd<7:0> pmenb pmrd/pmwr pmcs1 pma<1> pma<10:2> (1) pmall pmalh pma<7:0> pma<10:8> eeprom address bus data bus control lines dspic33f lcd fifo microcontroller 8-bit data up to 11-bit address parallel master port buffer note 1: 28-pin devices do not have pma<10:2>. pma<14> downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 308 ? 2007-2012 microchip technology inc. 26.1 pmp resources many useful resources rela ted to pmp are provided on the main product page of the microchip web site for the devices listed in this data sheet. this product page, which can be accessed using this link , contains the latest updates and additional information. 26.1.1 key resources section 35. parallel master port (pmp) (ds70299) code samples application notes software libraries webinars all related dspic33f/pic24h family reference manuals sections development tools note: in the event you are not able to access the product page using t he link above, enter this url in your browser: http://www.microchip.com/wwwproducts/ devices.aspx?ddocname=en532311 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 309 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 26.2 pmp control registers register 26-1: pmcon: parallel master port control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmpen psidl adrmux1 adrmux0 ptbeen ptwren ptrden bit 15 bit 8 r/w-0 r/w-0 r/w-0 (1) u-0 r/w-0 (1) r/w-0 r/w-0 r/w-0 csf1 csf0 alp cs1p bep wrsp rdsp bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 pmpen: parallel master port enable bit 1 = pmp enabled 0 = pmp disabled, no off-chip access performed bit 14 unimplemented: read as 0 bit 13 psidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux1:adrmux0: address/data multiplexing selection bits (1) 11 = reserved 10 = all 16 bits of address are multiplexed on pmd<7:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper 3 bits are multiplexed on pma<10:8> 00 = address and data appear on separate pins bit 10 ptbeen: byte enable port enable bit (16-bit master mode) 1 = pmbe port enabled 0 = pmbe port disabled bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port enabled 0 = pmwr/pmenb port disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port enabled 0 = pmrd/pmwr port disabled bit 7-6 csf1:csf0: chip select function bits 11 = reserved 10 = pmcs1 functions as chip select 0x = pmcs1 functions as address bit 14 bit 5 alp: address latch polarity bit (1) 1 = active-high (pmall and pmalh) 0 = active-low (pmall and pmalh ) bit 4 unimplemented: read as 0 bit 3 cs1p: chip select 1 polarity bit (1) 1 = active-high (pmcs1/pmcs1) 0 = active-low (pmcs1 /pmcs1 ) note 1: these bits have no effect when their corresponding pins are used as address lines. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 310 ? 2007-2012 microchip technology inc. bit 2 bep: byte enable polarity bit 1 = byte enable active-high (pmbe) 0 = byte enable active-low (pmbe ) bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = write strobe active-high (pmwr) 0 = write strobe active-low (pmwr ) for master mode 1 (pmmode<9:8> = 11 ): 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low (pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00,01,10 ): 1 = read strobe active-high (pmrd) 0 = read strobe active-low (pmrd ) for master mode 1 (pmmode<9:8> = 11 ): 1 = read/write strobe active-high (pmrd/pmwr ) 0 = read/write strobe active-low (pmrd /pmwr) register 26-1: pmcon: parallel master port control register (continued) note 1: these bits have no effect when their corresponding pins are used as address lines. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 311 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 26-2: pmmode: parallel port mode register r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1) waitm<3:0> waite<1:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 busy: busy bit (master mode only) 1 = port is busy (not useful wh en the processor stall is active) 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) or on a read or write operation when pma<1:0> = 11 (addressable psp mode only) 10 = no interrupt generated, processor stall activated 01 = interrupt generated at t he end of the read/write cycle 00 = no interrupt generated bit 12-11 incm<1:0>: increment mode bits 11 = psp read and write buffers auto-increment (legacy psp mode only) 10 = decrement addr<10:0> by 1 every read/write cycle 01 = increment addr<10:0> by 1 every read/write cycle 00 = no increment or decrement of address bit 10 mode16: 8-bit/16-bit mode bit 1 = 16-bit mode: data register is 16 bits, a read or wr ite to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bi ts, a read or write to the data register invokes one 8-bit transfer bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcs1, pmrd/pmwr , pmenb, pmbe, pma dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 312 ? 2007-2012 microchip technology inc. register 26-3: pmaddr: para llel port address register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr15 cs1 addr<13:8> bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 addr15: parallel port dest ination address bits bit 14 cs1: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive bit 13-0 addr13:addr0: parallel port destination address bits register 26-4: pmaen: parallel port enable register u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 p t e n 1 4 pten<10:8> (1) bit 15 bit 8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:2> (1) pten<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 unimplemented: read as 0 bit 14 pten14: pmcs1 strobe enable bit 1 = pma14 functions as either pma<14> bit or pmcs1 0 = pma14 pin functions as port i/o bit 13-11 unimplemented: read as 0 bit 10-2 pten<10:2>: pmp address port enable bits (1) 1 = pma<10:2> function as pmp address lines 0 = pma<10:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall 0 = pma1 and pma0 pads functions as port i/o note 1: devices with 28 pins do not have pma<10:2>. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 313 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 register 26-5: pmstat: parallel port status register r-0 r/w-0, hs u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ib3f ib2f ib1f ib0f bit 15 bit 8 r-1 r/w-0, hs u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ob3e ob2e ob1e ob0e bit 7 bit 0 legend: hs = hardware set bit r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte regi ster occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as 0 bit 11-8 ib3f:ib0f: input buffer x status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable ou tput buffer registers are full bit 6 obuf: output buffer underflow status bits 1 = a read occurred from an empty output by te register (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as 0 bit 3-0 ob3e:ob0e: output buffer x status empty bit 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 314 ? 2007-2012 microchip technology inc. register 26-6: padcfg1: pad co nfiguration control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 rtsecsel (1) pmpttl bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 15-2 unimplemented: read as 0 bit 1 rtsecsel: rtcc seconds clock output select bit (1) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 0 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffers note 1: to enable the actual rtcc output, the rtcoe bit (rcfgcal<10>) needs to be set. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 315 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 27.0 special features dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. these are: flexible configuration watchdog timer (wdt) code protection and codeguard? security jtag boundary scan interface in-circuit serial programming? (icsp?) in-circuit emulation 27.1 configuration bits the dspic33fj32gp302/30 4, dspic33fj64gpx02/ x04, and dspic33fj128gpx 02/x04 devices provide nonvolatile memory implementation for device configuration bits. refer to section 25. device con- figuration (ds70194), in the dspic33f/pic24h family reference manual for more information on this implementation. the configuration bits can be programmed (read as 0 ), or left unprogrammed (read as 1 ), to select vari- ous device configurations. these bits are mapped starting at program memory location 0xf80000. the individual configuration bit descriptions for the configuration registers are shown in table 27-2 . note that address 0xf80000 is beyond the user program memory space. it belongs to the configuration memory space (0x800000-0xffffff), which can only be accessed using table reads and table writes. the device configuration register map is shown in table 27-1 . note 1: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference source. to comple- ment the information in this data sheet, refer to the dspic33f/pic24h family reference manual . please see the microchip web site ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual sections. 2: some registers and associated bits described in this section may not be avail- able on all devices. refer to section 4.0 memory organization in this data sheet for device-specif ic register and bit information. table 27-1: device configuration register map address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xf80000 fbs rbs<1:0> bss<2:0> bwrp 0xf80002 fss (1) rss<1:0> sss<2:0> swrp 0xf80004 fgs gss<1:0> gwrp 0xf80006 foscsel ieso f n o s c < 2 : 0 > 0xf80008 fosc fcksm<1:0> iol1way osciofnc poscmd<1:0> 0xf8000a fwdt fwdten windis wdtpre wdtpost<3:0> 0xf8000c fpor reserved (2) alti2c f p w r t < 2 : 0 > 0xf8000e ficd reserved (3) jtagen i c s < 1 : 0 > 0xf80010 fuid0 user unit id byte 0 0xf80012 fuid1 user unit id byte 1 0xf80014 fuid2 user unit id byte 2 0xf80016 fuid3 user unit id byte 3 legend: = unimplemented bit, read as 0 . note 1: this configuration register is not available a nd reads as 0xff on dspic33fj32gp302/304 devices. 2: these bits are reserved and always read as 1 . 3: these bits are reserved for use by development tools and must be programmed as 1 . downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 316 ? 2007-2012 microchip technology inc. table 27-2: dspic config uration bits description bit field register rtsp effect description bwrp fbs immediate boot segment program flash write protection 1 = boot segment can be written 0 = boot segment is write-protected bss<2:0> fbs immediate boot segment pr ogram flash code protection size x11 = no boot program flash segment boot space is 1k instruction words (except interrupt vectors) 110 = standard security; boot pr ogram flash segment ends at 0x0007fe 010 = high security; boot program flash segment ends at 0x0007fe boot space is 4k instruction words (except interrupt vectors) 101 = standard security; boot program flash segment, ends at 0x001ffe 001 = high security; boot program flash segment ends at 0x001ffe boot space is 8k instruction words (except interrupt vectors) 100 = standard security; boot pr ogram flash segment ends at 0x003ffe 000 = high security; boot program flash segment ends at 0x003ffe rbs<1:0> (1) fbs immediate boot segment ram code protection size 11 = no boot ram defined 10 = boot ram is 128 bytes 01 = boot ram is 256 bytes 00 = boot ram is 1024 bytes swrp (1) fss (1) immediate secure segment program flash write-protect bit 1 = secure segment can bet written 0 = secure segment is write-protected sss<2:0> (1) fss (1) immediate secure segment program flash code protection size (secure segment is not implemented on 32k devices) x11 = no secure program flash segment secure space is 4k iw less bs 110 = standard security; secure program flash segment starts at end of bs, ends at 0x001ffe 010 = high security; secure prog ram flash segment starts at end of bs, ends at 0x001ffe secure space is 8k iw less bs 101 = standard security; secure program flash segment starts at end of bs, ends at 0x003ffe 001 = high security; secure prog ram flash segment starts at end of bs, ends at 0x003ffe secure space is 16k iw less bs 100 = standard security; secure program flash segment starts at end of bs, ends at 007ffeh 000 = high security; secure prog ram flash segment starts at end of bs, ends at 0x007ffe note 1: this configuration register is not av ailable on dspic33fj32gp302/304 devices. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 317 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 rss<1:0> (1) fss (1) immediate secure segment ram code protection 11 = no secure ram defined 10 = secure ram is 256 bytes less bs ram 01 = secure ram is 2048 bytes less bs ram 00 = secure ram is 4096 bytes less bs ram gss<1:0> fgs immediate general segment code-protect bit 11 = user program memory is not code-protected 10 = standard security 0x = high security gwrp fgs immediate general segment write-protect bit 1 = user program memory is not write-protected 0 = user program memory is write-protected ieso foscsel immediate two-speed o scillator start-up enable bit 1 = start-up device with frc, then au tomatically switch to the user-selected oscillator source when ready 0 = start-up device with user-selected oscillator source fnosc<2:0> foscsel if clock switch is enabled, rtsp effect is on any device reset; otherwise, immediate initial oscillator source selection bits 111 = internal fast rc (frc) oscillator with postscaler 110 = internal fast rc (frc) oscillator with divide-by-16 101 = lprc oscillator 100 = secondary (lp) oscillator 011 = primary (xt, hs, ec) oscillator with pll 010 = primary (xt, hs, ec) oscillator 001 = internal fast rc (frc) oscillator with pll 000 = frc oscillator fcksm<1:0> fosc immediate clock switching mode bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabl ed, fail-safe clock monitor is disabled 00 = clock switching is enabl ed, fail-safe clock monitor is enabled iol1way fosc immediate peripheral pin select configuration 1 = allow only one reconfiguration 0 = allow multiple reconfigurations osciofnc fosc immediate osc2 pin function bit (except in xt and hs modes) 1 = osc2 is clock output 0 = osc2 is general purpose digital i/o pin poscmd<1:0> fosc immediate primary oscillator mode select bits 11 = primary oscillator disabled 10 = hs crystal oscillator mode 01 = xt crystal oscillator mode 00 = ec (external clock) mode fwdten fwdt immediate watchdog timer enable bit 1 = watchdog timer always enabled (lprc oscillator cannot be disabled. clearing the swdten bit in the rcon register has no effect.) 0 = watchdog timer enabled/disabled by user software (lprc can be disabled by clearing the swdten bit in the rcon register) windis fwdt immediate watchdog timer window enable bit 1 = watchdog timer in non-window mode 0 = watchdog timer in window mode table 27-2: dspic configuratio n bits description (continued) bit field register rtsp effect description note 1: this configuration register is not available on dspic33fj32gp302/304 devices. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 318 ? 2007-2012 microchip technology inc. wdtpre fwdt immediate watchdog timer prescaler bit 1 = 1:128 0 = 1:32 wdtpost<3:0> fwdt immediate watchdog timer postscaler bits 1111 = 1:32,768 1110 = 1:16,384 0001 = 1:2 0000 = 1:1 fpwrt<2:0> fpor immediate power-on reset timer value select bits 111 = pwrt = 128 ms 110 = pwrt = 64 ms 101 = pwrt = 32 ms 100 = pwrt = 16 ms 011 = pwrt = 8 ms 010 = pwrt = 4 ms 001 = pwrt = 2 ms 000 = pwrt = disabled alti2c fpor immediate alternate i 2 c? pins 1 = i 2 c mapped to sda1/scl1 pins 0 = i 2 c mapped to asda1/ascl1 pins jtagen ficd immediate jtag enable bit 1 = jtag enabled 0 = jtag disabled ics<1:0> ficd immediate icd communication channel select bits 11 = communicate on pgec1 and pged1 10 = communicate on pgec2 and pged2 01 = communicate on pgec3 and pged3 00 = reserved, do not use table 27-2: dspic configuratio n bits description (continued) bit field register rtsp effect description note 1: this configuration register is not av ailable on dspic33fj32gp302/304 devices. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 319 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 27.2 on-chip voltage regulator all of the dspi c33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 devices power their core digital logic at a nominal 2.5v. this can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system de sign, all devices in the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 family incorporate an on-chip regulator that allows the device to run its core logic from v dd . the regulator provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr (less than 5 ohms) capacitor (such as tantalum or ceramic) must be connected to the v cap pin ( figure 27-1 ). this helps to maintain the stability of the regulator. the recommended value for the filter capac- itor is provided in table 30-13 located in section 30.1 dc characteristics . on a por , it takes approximately 20 s for the on-chip voltage regulator to generate an output voltage. during this time, designated as t startup , code execution is disabled. t startup is applied every time the device resumes operation after any power-down. figure 27-1: connections for the on-chip voltage regulator (1,2,3) 27.3 bor: brown-out reset the brown-out reset (bor) module is based on an internal voltage reference circuit that monitors the reg- ulated supply voltage v cap . the main purpose of the bor module is to generate a device reset when a brown-out condition occurs. brown-out conditions are generally caused by glitches on the ac mains (for example, missing portions of the ac cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). a bor generates a reset pulse, which resets the device. the bor selects the clock source, based on the device configuration bit values (fnosc<2:0> and poscmd<1:0>). if an oscillator mode is selected, the bor activates the oscillator start-up timer (o st). the system clock is held until ost expires. if the pll is used, the clock is held until the lock bit (osccon<5>) is 1 . concurrently, the pwrt time -out (tpwrt) is applied before the internal reset is released. if tpwrt = 0 and a crystal oscillator is being used, then a nominal delay of tfscm = 100 is applied. the total delay in this case is tfscm. the bor status bit (rcon<1>) is set to indicate that a bor has occurred. the bor circuit continues to oper- ate while in sleep or idle modes and resets the device should vdd fall below the bor threshold voltage. note: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. note 1: these are typical operating voltages. refer to table 30-13 , located in section 30.1 dc characteristics for the full operating ranges of v dd and v cap . 2: it is important for the low-esr capacitor to be placed as close as possible to the v cap pin. 3: typical v cap pin voltage = 2.5v when v dd v ddmin . v dd v cap v ss dspic33f c efc 3.3v 10 f tantalum downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 320 ? 2007-2012 microchip technology inc. 27.4 watchdog timer (wdt) for dspic33fj32gp302/3 04, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 devices, the wdt is driven by the lprc o scillator. when the wdt is enabled, the clock source is also enabled. 27.4.1 prescaler/postscaler the nominal wdt clock source from lprc is 32 khz. this feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. the prescaler is set by the wdtpre configuration bit. with a 32 khz input, the prescaler yields a nominal wdt time-out period (t wdt ) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. a variable postscaler divides down the wdt prescaler output and allows for a wide range of time-out periods. the postscaler is controlled by the wdtpost<3:0> configuration bits (fwdt<3:0>), which allow the selec- tion of 16 settings, from 1:1 to 1:32,768. using the pres- caler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. the wdt, prescaler and postscaler are reset: on any form of device reset on the completion of a clock switch, whether invoked by software (i.e., setting the oswen bit after changing the nosc bits) or by hardware (i.e., fail-safe clock monitor) when a pwrsav instruction is executed (i.e., sleep or idle mode is entered) when the device exits sleep or idle mode to resume normal operation by a clrwdt instruction during normal execution 27.4.2 sleep and idle modes if the wdt is enabled, it continues to run during sleep or idle modes. when the wdt time-out occurs, the device wakes the device and code execution continues from where the pwrsav instruction was executed. the corre- sponding sleep or idle bits (rcon<3,2>) needs to be cleared in software afte r the device wakes up. 27.4.3 enabling wdt the wdt is enabled or disabled by the fwdten configuration bit in the fwdt configuration register. when the fwdten configuration bit is set, the wdt is always enabled. the wdt can be optionally controlled in software when the fwdten configuration bit has been programmed to 0 . the wdt is enabled in software by setting the swdten co ntrol bit (rcon<5>). the swdten control bit is cleared on any device reset. the software wdt option allows the user application to enable the wdt for critical code segments and disable the wdt during non-critical segments for maximum power savings. the wdt flag, wdto bit (rcon< 4>), is not automatically cleared following a wdt time-out. to detect subsequent wdt events, the flag must be cleared in software. figure 27-2: wdt block diagram note: the clrwdt and pwrsav instructions clear the prescaler and postscaler counts when executed. note: if the windis bit (fwdt<6>) is cleared, the clrwdt instruction should be executed by the application software only during the last 1/4 of the wdt period. this clrwdt win- dow can be determined by using a timer. if a clrwdt instruction is executed before this window, a wdt reset occurs. all device resets transition to new clock source exit sleep or idle mode pwrsav instruction clrwdt instruction 0 1 wdtpre wdtpost<3:0> watchdog timer prescaler (divide by n1) postscaler (divide by n2) sleep/idle wdt wdt window select windis wdt clrwdt instruction swdten fwdten lprc clock rs rs wake-up reset downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 321 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 27.5 jtag interface dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 devices implement a jtag interface, which supports boundary scan device testing, as well as in-circuit programming. detailed information on this interface is provided in future revisions of the document. 27.6 in-circuit serial programming? (icsp)? the dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128g px02/x04 devices can be serially programmed while in the end application circuit. this is done with two lines for clock and data and three other lines for power, ground and the programming sequence. serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. serial programming also allows the most recent firmware or a custom firmware to be programmed. refer to the dspic33f/pic24h flash programming specification (ds70152) for details about in-circuit serial programming (icsp). any of the three pairs of programming clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 27.7 in-circuit debugger when mplab ? icd 3 is selected as a debugger, the in- circuit debugging functionality is enabled. this function allows simple debugging functions when used with mplab ide. debugging functionality is controlled through the pgecx (emulation/debug clock) and pgedx (emulation/debug data) pin functions. any of the three pairs of debugging clock/data pins can be used: pgec1 and pged1 pgec2 and pged2 pgec3 and pged3 to use the in-circuit debugger function of the device, the design must implement icsp connections to mclr , v dd , v ss , pgc, pgd and the pgecx and pgedx pin pairs. in addition, when the feature is enabled, some of the resources are not available for general use. these resources include the first 80 bytes of data ram and two i/o pins. 27.8 code protection and codeguard? security the dspic33fj64gpx02/x04 and dspic33fj128gpx02/x04 devices offer advanced implementation of codeguard security that supports bs, ss and gs while, the dspic33fj32gp302/304 devices offer the intermediate level of codeguard security that supports only bs and gs. codeguard security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. this feature helps protect individual intellectual property in collaborative system designs. when coupled with software encryption libraries, codeguard security can be used to securely update flash even when multiple ips reside on the single chip. the code protection featur es vary depending on the actual dspic33f implemented. the following sections provide an overview of these features. secure segment and ram protection is implemented on the dspic33fj64gpx02/x04 and dspic33fj128gpx02/x04 devices. the dspic33fj32gp302/304 devices do not support secure segment and ram protection. note: refer to section 24. programming and diagnostics (ds70207) of the dspic33f/pic24h family reference manual for further information on usage, configuration and operation of the jtag interface. note: refer to section 23. codeguard? security (ds70199) of the dspic33f/ pic24h family reference manual for further information on usage, configuration and operation of codeguard security. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 322 ? 2007-2012 microchip technology inc. table 27-3: code flash security se gment sizes for 32 kb devices config bits bss<2:0> = x11 0k bss<2:0> = x10 1k bss<2:0> = x01 4k bss<2:0> = x00 8k sss<2:0> = x11 0k 0x0057feh 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x001ffeh 0x002000h gs = 11008 iw 0x0157feh 0x0057feh 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x001ffeh 0x002000h 0x0157feh gs = 10240 iw bs = 768 iw vs = 256 iw gs = 7168 iw bs = 3840 iw 0x0057feh 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 3072 iw bs = 7936 iw 0x0057feh 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x001ffeh 0x002000h 0x0157feh downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 323 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 27-4: code flash security se gment sizes for 64 kb devices config bits bss<2:0> = x11 0k bss<2:0> = x10 1k bss<2:0> = x01 4k bss<2:0> = x00 8k sss<2:0> = x11 0k sss<2:0> = x10 4k sss<2:0> = x01 8k sss<2:0> = x00 16k 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h gs = 21760 iw 0x0157feh vs = 256 iw gs = 20992 iw bs = 768 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 17920 iw bs = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 17920 iw ss = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 17920 iw bs = 768 iw ss = 3072 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 17920 iw bs = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw ss = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw bs = 768 iw ss = 7168 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw bs = 3840 iw ss = 4096 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 13824 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 5632 iw ss = 16128 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 5632 iw bs = 768 iw ss = 15360 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 5632 iw bs = 3840 iw ss = 12288 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh vs = 256 iw gs = 5632 iw bs = 7936 iw ss = 8192 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 324 ? 2007-2012 microchip technology inc. table 27-5: code flash security se gment sizes for 128 kb devices config bits bss<2:0> = x11 0k bss<2:0> = x10 1k bss<2:0> = x01 4k bss<2:0> = x00 8k sss<2:0> = x11 0k sss<2:0> = x10 4k sss<2:0> = x01 8k sss<2:0> = x00 16k 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 43776 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 43008 iw bs = 768 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 39936 iw bs = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh gs = 39936 iw ss = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh gs = 39936 iw bs = 768 iw ss = 3072 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh gs = 39936 iw bs = 3840 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00abfeh 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw ss = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw bs = 768 iw ss = 7168 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw bs = 3840 iw ss = 4096 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 35840 iw bs = 7936 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 27648 iw ss = 16128 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 27648 iw bs = 768 iw ss = 15360 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 27648 iw bs = 3840 iw ss = 12288 iw 0x007ffeh 0x008000h 0x003ffeh 0x004000h 0x0001feh 0x000200h 0x000000h vs = 256 iw 0x0007feh 0x000800h 0x00fffeh 0x010000h 0x001ffeh 0x002000h 0x0157feh gs = 27648 iw bs = 7936 iw ss = 8192 iw downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 325 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 28.0 instruction set summary the dspic33f instruction set is identical to that of the dspic30f. most instructions are a single program memory word (24 bits). only three instructions require two program memory locations. each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more oper ands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into five basic categories: word or byte-oriented operations bit-oriented operations literal operations dsp operations control operations table 28-1 shows the general symbols used in describing the instructions. the dspic33f instruct ion set summary in ta b l e 2 8 - 2 lists all the instructions, along with the status flags affected by each instruction. most word or byte-oriente d w register instructions (including barrel shift instructions) have three operands: the first source operand, which is typically a register wb without any address modifier the second source operand, which is typically a register ws with or without an address modifier the destination of the result, which is typically a register wd with or without an address modifier however, word or byte-oriented file register instructions have two operands: the file register specified by the value f the destination, which c ould be either the file register f or the w0 regi ster, which is denoted as wreg most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: the w register (with or without an address modifier) or file register (specified by the value of ws or f) the bit in the w register or file register (specified by a literal value or indire ctly by the contents of register wb) the literal instructions that involve data movement can use some of the following operands: a literal value to be loaded into a w register or file register (specified by k) the w register or file register where the literal value is to be loaded (specified by wb or f) however, literal instructions that involve arithmetic or logical operations use some of the following operands: the first source operand, which is a register wb without any address modifier the second source operand, which is a literal value the destination of the result (only if not the same as the first source operand), which is typically a register wd with or without an address modifier the mac class of dsp instructions can use some of the following operands: the accumulator (a or b) to be used (required operand) the w registers to be used as the two operands the x and y address space prefetch operations the x and y address space prefetch destinations the accumulator write back destination the other dsp instructions do not involve any multiplication and can include: the accumulator to be used (required) the source or destination operand (designated as wso or wdo, respectively) with or without an address modifier the amount of shift specif ied by a w register wn or a literal value the control instructions can use some of the following operands: a program memory address the mode of the table read and table write instructions note: this data sheet summarizes the features of the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 families of devices. it is not intended to be a compre- hensive reference s ource. to complement the information in this data sheet, refer to the dspic33f/pic24h family reference manual . please see the microchip web site ( www.microchip.com ) for the latest reference manual sections. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 326 ? 2007-2012 microchip technology inc. most instructions are a single word. certain double- word instructions are designed to provide all the required information in these 48 bits. in the second word, the 8 msbs are 0 s. if this second word is executed as an instruction (by itself), it executes as a nop . the double-word instructions execute in two instruction cycles. most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . notable exceptions are the bra (unconditional/computed branch), indirect call/goto , all table reads and writes and return/retfie instruc- tions, which are single-word instructions but take two or three cycles. certain instru ctions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. moreover, double-word moves require two cycles. note: for more details on the instruction set, refer to the 16-bit mcu and dsc programmers reference manual (ds70157). table 28-1: symbols used in opcode descriptions field description #text means literal defined by text (text) means content of text [text] means the location addressed by text { } optional field or operation ? 2007-2012 microchip tec hnology inc. ds70292g-page 327 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 wm*wm multiplicand and multiplier working register pair for square instructions {w4 * w4,w5 * w5,w6 * w6,w7 * w7} wm*wn multiplicand and multiplier working register pair for dsp instructions {w4 * w5,w4 * w6,w4 * w7,w5 * w6,w5 * w7,w6 * w7} wn one of 16 working registers {w0...w15} wnd one of 16 destination working registers {w0...w15} wns one of 16 source working registers {w0...w15} wreg w0 (working register used in file register instructions) ws source w register { ws, [ws], [ws++], [ws --], [++ws], [--ws] } wso source w register { wns, [wns], [wns++], [wns--], [++wns], [--wns], [wns+wb] } wx x data space prefetch address register for dsp instructions {[w8] + = 6, [w8] + = 4, [w8] + = 2, [w8], [w8] - = 6, [w8] - = 4, [w8] - = 2, [w9] + = 6, [w9] + = 4, [w9] + = 2, [w9], [w9] - = 6, [w9] - = 4, [w9] - = 2, [w9 + w12], none} wxd x data space prefetch destinati on register for dsp instructions {w4...w7} wy y data space prefetch address register for dsp instructions {[w10] + = 6, [w10] + = 4, [w10] + = 2, [w10], [w10] - = 6, [w10] - = 4, [w10] - = 2, [w11] + = 6, [w11] + = 4, [w11] + = 2, [w11], [w11] - = 6, [w11] - = 4, [w11] - = 2, [w11 + w12], none} wyd y data space prefetch destination register for dsp instructions {w4...w7} table 28-1: symbols used in opcode descriptions (continued) field description downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 328 ? 2007-2012 microchip technology inc. table 28-2: instruction set overview base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected 1 add add acc add accumulators 1 1 oa,ob,sa,sb add f f = f + wreg 1 1 c,dc,n,ov,z add f,wreg wreg = f + wreg 1 1 c,dc,n,ov,z add #lit10,wn wd = lit10 + wd 1 1 c,dc,n,ov,z add wb,ws,wd wd = wb + ws 1 1 c,dc,n,ov,z add wb,#lit5,wd wd = wb + lit5 1 1 c,dc,n,ov,z add wso,#slit4,acc 16-bit signed add to accumulator 1 1 oa,ob,sa,sb 2 addc addc f f = f + wreg + (c) 1 1 c,dc,n,ov,z addc f,wreg wreg = f + wreg + (c) 1 1 c,dc,n,ov,z addc #lit10,wn wd = lit10 + wd + (c) 1 1 c,dc,n,ov,z addc wb,ws,wd wd = wb + ws + (c) 1 1 c,dc,n,ov,z addc wb,#lit5,wd wd = wb + lit5 + (c) 1 1 c,dc,n,ov,z 3 and and f f = f .and. wreg 1 1 n,z and f,wreg wreg = f .and. wreg 1 1 n,z and #lit10,wn wd = lit10 .and. wd 1 1 n,z and wb,ws,wd wd = wb .and. ws 1 1 n,z and wb,#lit5,wd wd = wb .and. lit5 1 1 n,z 4 asr asr f f = arithmetic right shift f 1 1 c,n,ov,z asr f,wreg wreg = arithmetic right shift f 1 1 c,n,ov,z asr ws,wd wd = arithmetic right shift ws 1 1 c,n,ov,z asr wb,wns,wnd wnd = arithmetic right shift wb by wns 1 1 n,z asr wb,#lit5,wnd wnd = arithmetic right shift wb by lit5 1 1 n,z 5 bclr bclr f,#bit4 bit clear f 1 1 none bclr ws,#bit4 bit clear ws 1 1 none 6 bra bra c,expr branch if carry 1 1 (2) none bra ge,expr branch if greater than or equal 1 1 (2) none bra geu,expr branch if unsigned greater than or equal 1 1 (2) none bra gt,expr branch if greater than 1 1 (2) none bra gtu,expr branch if unsigned greater than 1 1 (2) none bra le,expr branch if less than or equal 1 1 (2) none bra leu,expr branch if unsigned less than or equal 1 1 (2) none bra lt,expr branch if less than 1 1 (2) none bra ltu,expr branch if unsigned less than 1 1 (2) none bra n,expr branch if negative 1 1 (2) none bra nc,expr branch if not carry 1 1 (2) none bra nn,expr branch if not negative 1 1 (2) none bra nov,expr branch if not overflow 1 1 (2) none bra nz,expr branch if not zero 1 1 (2) none bra oa,expr branch if accumulator a overflow 1 1 (2) none bra ob,expr branch if accumulator b overflow 1 1 (2) none bra ov,expr branch if overflow 1 1 (2) none bra sa,expr branch if accumulator a saturated 1 1 (2) none bra sb,expr branch if accumulator b saturated 1 1 (2) none bra expr branch unconditionally 1 2 none bra z,expr branch if zero 1 1 (2) none bra wn computed branch 1 2 none 7 bset bset f,#bit4 bit set f 1 1 none bset ws,#bit4 bit set ws 1 1 none 8 bsw bsw.c ws,wb write c bit to ws ? 2007-2012 microchip tec hnology inc. ds70292g-page 329 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 10 btsc btsc f,#bit4 bit test f, skip if clear 1 1 (2 or 3) none btsc ws,#bit4 bit test ws, skip if clear 1 1 (2 or 3) none 11 btss btss f,#bit4 bit test f, skip if set 1 1 (2 or 3) none btss ws,#bit4 bit test ws, skip if set 1 1 (2 or 3) none 12 btst btst f,#bit4 bit test f 1 1 z btst.c ws,#bit4 bit test ws to c 1 1 c btst.z ws,#bit4 bit test ws to z 1 1 z btst.c ws,wb bit test ws dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 330 ? 2007-2012 microchip technology inc. 29 div div.s wm,wn signed 16/16-bit integer divide 1 18 n,z,c,ov div.sd wm,wn signed 32/16-bit integer divide 1 18 n,z,c,ov div.u wm,wn unsigned 16/16-bit integer divide 1 18 n,z,c,ov div.ud wm,wn unsigned 32/16-bit integer divide 1 18 n,z,c,ov 30 divf divf wm,wn signed 16/16-bit fractional divide 1 18 n,z,c,ov 31 do do #lit14,expr do code to pc + expr, lit14 + 1 times 2 2 none do wn,expr do code to pc + expr, (wn) + 1 times 2 2 none 32 ed ed wm*wm,acc,wx,wy,wxd euclidean distance (no accumulate) 1 1 oa,ob,oab, sa,sb,sab 33 edac edac wm*wm,acc,wx,wy,wxd euclidean distance 1 1 oa,ob,oab, sa,sb,sab 34 exch exch wns,wnd swap wns with wnd 1 1 none 35 fbcl fbcl ws,wnd find bit change from left (msb) side 1 1 c 36 ff1l ff1l ws,wnd find first one from left (msb) side 1 1 c 37 ff1r ff1r ws,wnd find first one from right (lsb) side 1 1 c 38 goto goto expr go to address 2 2 none goto wn go to indirect 1 2 none 39 inc inc f f = f + 1 1 1 c,dc,n,ov,z inc f,wreg wreg = f + 1 1 1 c,dc,n,ov,z inc ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 40 inc2 inc2 f f = f + 2 1 1 c,dc,n,ov,z inc2 f,wreg wreg = f + 2 1 1 c,dc,n,ov,z inc2 ws,wd wd = ws + 2 1 1 c,dc,n,ov,z 41 ior ior f f = f .ior. wreg 1 1 n,z ior f,wreg wreg = f .ior. wreg 1 1 n,z ior #lit10,wn wd = lit10 .ior. wd 1 1 n,z ior wb,ws,wd wd = wb .ior. ws 1 1 n,z ior wb,#lit5,wd wd = wb .ior. lit5 1 1 n,z 42 lac lac wso,#slit4,acc load accumulator 1 1 oa,ob,oab, sa,sb,sab 43 lnk lnk #lit14 link frame pointer 1 1 none 44 lsr lsr f f = logical right shift f 1 1 c,n,ov,z lsr f,wreg wreg = logical right shift f 1 1 c,n,ov,z lsr ws,wd wd = logical right shift ws 1 1 c,n,ov,z lsr wb,wns,wnd wnd = logical right shift wb by wns 1 1 n,z lsr wb,#lit5,wnd wnd = logical right shift wb by lit5 1 1 n,z 45 mac mac wm*wn,acc,wx,wxd,wy,wyd , awb multiply and accumulate 1 1 oa,ob,oab, sa,sb,sab mac wm*wm,acc,wx,wxd,wy,wyd square and accumulate 1 1 oa,ob,oab, sa,sb,sab 46 mov mov f,wn move f to wn 1 1 none mov f move f to f 1 1 none mov f,wreg move f to wreg 1 1 n,z mov #lit16,wn move 16-bit literal to wn 1 1 none mov.b #lit8,wn move 8-bit literal to wn 1 1 none mov wn,f move wn to f 1 1 none mov wso,wdo move ws to wd 1 1 none mov wreg,f move wreg to f 1 1 none mov.d wns,wd move double from w(ns):w(ns + 1) to wd 1 2 none mov.d ws,wnd move double from ws to w(nd + 1):w(nd) 1 2 none 47 movsac movsac acc,wx,wxd,wy,wyd,awb prefetch and store accumulator 1 1 none table 28-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 331 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 48 mpy mpy wm*wn,acc,wx,wxd,wy,wyd multiply wm by wn to accumulator 1 1 oa,ob,oab, sa,sb,sab mpy wm*wm,acc,wx,wxd,wy,wyd square wm to accumulator 1 1 oa,ob,oab, sa,sb,sab 49 mpy.n mpy.n wm*wn,acc,wx,wxd,wy,wyd -(multiply wm by wn) to accumulator 1 1 none 50 msc msc wm*wm,acc,wx,wxd,wy,wyd , awb multiply and subtract from accumulator 1 1 oa,ob,oab, sa,sb,sab 51 mul mul.ss wb,ws,wnd {wnd + 1, wnd} = signed(wb) * signed(ws) 1 1 none mul.su wb,ws,wnd {wnd + 1, wnd} = signed(wb) * unsigned(ws) 1 1 none mul.us wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * signed(ws) 1 1 none mul.uu wb,ws,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(ws) 1 1 none mul.su wb,#lit5,wnd {wnd + 1, wnd} = signed(wb) * unsigned(lit5) 1 1 none mul.uu wb,#lit5,wnd {wnd + 1, wnd} = unsigned(wb) * unsigned(lit5) 1 1 none mul f w3:w2 = f * wreg 1 1 none 52 neg neg acc negate accumulator 1 1 oa,ob,oab, sa,sb,sab neg f f = f + 1 1 1 c,dc,n,ov,z neg f,wreg wreg = f + 1 1 1 c,dc,n,ov,z neg ws,wd wd = ws + 1 1 1 c,dc,n,ov,z 53 nop nop no operation 1 1 none nopr no operation 1 1 none 54 pop pop f pop f from top-of-stack (tos) 1 1 none pop wdo pop from top-of-stack (tos) to wdo 1 1 none pop.d wnd pop from top-of-stack (tos) to w(nd):w(nd + 1) 1 2 none pop.s pop shadow registers 1 1 all 55 push push f push f to top-of-stack (tos) 1 1 none push wso push wso to top-of-stack (tos) 1 1 none push.d wns push w(ns):w(ns + 1) to top-of-stack (tos) 1 2 none push.s push shadow registers 1 1 none 56 pwrsav pwrsav #lit1 go into sleep or idle mode 1 1 wdto,sleep 57 rcall rcall expr relative call 1 2 none rcall wn computed call 1 2 none 58 repeat repeat #lit14 repeat next instruction lit14 + 1 times 1 1 none repeat wn repeat next instruction (wn) + 1 times 1 1 none 59 reset reset software device reset 1 1 none 60 retfie retfie return from interrupt 1 3 (2) none 61 retlw retlw #lit10,wn return with literal in wn 1 3 (2) none 62 return return return from subroutine 1 3 (2) none 63 rlc rlc f f = rotate left through carry f 1 1 c,n,z rlc f,wreg wreg = rotate left through carry f 1 1 c,n,z rlc ws,wd wd = rotate left through carry ws 1 1 c,n,z 64 rlnc rlnc f f = rotate left (no carry) f 1 1 n,z rlnc f,wreg wreg = rotate left (no carry) f 1 1 n,z rlnc ws,wd wd = rotate left (no carry) ws 1 1 n,z 65 rrc rrc f f = rotate right through carry f 1 1 c,n,z rrc f,wreg wreg = rotate right through carry f 1 1 c,n,z rrc ws,wd wd = rotate right through carry ws 1 1 c,n,z table 28-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 332 ? 2007-2012 microchip technology inc. 66 rrnc rrnc f f = rotate right (no carry) f 1 1 n,z rrnc f,wreg wreg = rotate right (no carry) f 1 1 n,z rrnc ws,wd wd = rotate right (no carry) ws 1 1 n,z 67 sac sac acc,#slit4,wdo store accumulator 1 1 none sac.r acc,#slit4,wdo store rounded accumulator 1 1 none 68 se se ws,wnd wnd = sign-extended ws 1 1 c,n,z 69 setm setm f f = 0xffff 1 1 none setm wreg wreg = 0xffff 1 1 none setm ws ws = 0xffff 1 1 none 70 sftac sftac acc,wn arithmetic shift accumulator by (wn) 1 1 oa,ob,oab, sa,sb,sab sftac acc,#slit6 arithmetic shift accumulator by slit6 1 1 oa,ob,oab, sa,sb,sab 71 sl sl f f = left shift f 1 1 c,n,ov,z sl f,wreg wreg = left shift f 1 1 c,n,ov,z sl ws,wd wd = left shift ws 1 1 c,n,ov,z sl wb,wns,wnd wnd = left shift wb by wns 1 1 n,z sl wb,#lit5,wnd wnd = left shift wb by lit5 1 1 n,z 72 sub sub acc subtract accumulators 1 1 oa,ob,oab, sa,sb,sab sub f f = f C wreg 1 1 c,dc,n,ov,z sub f,wreg wreg = f C wreg 1 1 c,dc,n,ov,z sub #lit10,wn wn = wn C lit10 1 1 c,dc,n,ov,z sub wb,ws,wd wd = wb C ws 1 1 c,dc,n,ov,z sub wb,#lit5,wd wd = wb C lit5 1 1 c,dc,n,ov,z 73 subb subb f f = f C wreg C (c ) 1 1 c,dc,n,ov,z subb f,wreg wreg = f C wreg C (c ) 1 1 c,dc,n,ov,z subb #lit10,wn wn = wn C lit10 C (c ) 1 1 c,dc,n,ov,z subb wb,ws,wd wd = wb C ws C (c ) 1 1 c,dc,n,ov,z subb wb,#lit5,wd wd = wb C lit5 C (c ) 1 1 c,dc,n,ov,z 74 subr subr f f = wreg C f 1 1 c,dc,n,ov,z subr f,wreg wreg = wreg C f 1 1 c,dc,n,ov,z subr wb,ws,wd wd = ws C wb 1 1 c,dc,n,ov,z subr wb,#lit5,wd wd = lit5 C wb 1 1 c,dc,n,ov,z 75 subbr subbr f f = wreg C f C (c ) 1 1 c,dc,n,ov,z subbr f,wreg wreg = wreg C f C (c ) 1 1 c,dc,n,ov,z subbr wb,ws,wd wd = ws C wb C (c ) 1 1 c,dc,n,ov,z subbr wb,#lit5,wd wd = lit5 C wb C (c ) 1 1 c,dc,n,ov,z 76 swap swap.b wn wn = nibble swap wn 1 1 none swap wn wn = byte swap wn 1 1 none 77 tblrdh tblrdh ws,wd read prog<23:16> to wd<7:0> 1 2 none 78 tblrdl tblrdl ws,wd read prog<15:0> to wd 1 2 none 79 tblwth tblwth ws,wd write ws<7:0> to prog<23:16> 1 2 none 80 tblwtl tblwtl ws,wd write ws to prog<15:0> 1 2 none 81 ulnk ulnk unlink frame pointer 1 1 none 82 xor xor f f = f .xor. wreg 1 1 n,z xor f,wreg wreg = f .xor. wreg 1 1 n,z xor #lit10,wn wd = lit10 .xor. wd 1 1 n,z xor wb,ws,wd wd = wb .xor. ws 1 1 n,z xor wb,#lit5,wd wd = wb .xor. lit5 1 1 n,z 83 ze ze ws,wnd wnd = zero-extend ws 1 1 c,z,n table 28-2: instruction set overview (continued) base instr # assembly mnemonic assembly syntax description # of words # of cycles status flags affected downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 333 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 29.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: integrated development environment - mplab ? ide software compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/link er/librarian for various device families simulators - mplab sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers - mplab icd 3 - pickit? 3 debug express device programmers - pickit? 2 programmer - mplab pm3 device programmer low-cost demonstratio n/development boards, evaluation kits, and starter kits 29.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color-coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection drag and drop variables from source to watch windows extensive on-line help integration of select thir d party tools, such as iar c compilers the mplab ide allows you to: edit your source files (either c or assembly) one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 334 ? 2007-2012 microchip technology inc. 29.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchips pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 29.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c comp ilers for microchips pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 29.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user-defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process 29.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 29.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 335 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 29.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 29.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 29.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 29.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and programming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial pr ogramming? (icsp)?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with users guide, lessons, tutorial, compiler and mplab ide software. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 336 ? 2007-2012 microchip technology inc. 29.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use interface for programming and debugging microchips flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchips powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcontrollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the applic ation. when halted at a breakpoint, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with users guide, lessons, tutorial, compiler and mplab ide software. 29.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpor ates an mmc card for file storage and data applications. 29.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstr ation, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, sw itches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 337 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 30.0 electrical characteristics this section provides an overview of dspic33fj32g p302/304, dspic33fj64gpx02/x 04, and dspic33fj128gpx02/ x04 electrical characteristics. additional information is prov ided in future revisions of this document as it becomes available. absolute maximum ratings for the dspic33fj32gp302/3 04, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 family are listed below. exposure to these maximum rating conditions for exte nded periods can affect device reliability. functional operation of the device at th ese or any other conditi ons above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss (4) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd 3.0v (4) .................................................. -0.3v to +5.6v voltage on any 5v tolerant pin with respect to vss when v dd < 3.0v (4) ...................................................... -0.3v to 3.6v maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin (2) ...........................................................................................................................250 ma maximum current sourced/sunk by any 2x i/o pin (3) ................................................................................................8 ma maximum current sourced/sunk by any 4x i/o pin (3) ..............................................................................................15 ma maximum current sourced/sunk by any 8x i/o pin (3) ..............................................................................................25 ma maximum current sunk by all ports ......................... ..................................................................... .........................200 ma maximum current sourced by all ports (2) ...............................................................................................................200 ma note 1: stresses above those listed under absolute maximu m ratings can cause permanent damage to the device. this is a stress rating only, and functional oper ation of the device at th ose or any other conditions above those indicated in the operation listings of this specification is not impl ied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 30-2 ). 3: exceptions are clkout, which is abl e to sink/source 25 ma, and the v ref +, v ref -, sclx, sdax, pgecx and pgedx pins, which are able to sink/source 12 ma. 4: see the pin diagrams section for 5v tolerant pins. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 338 ? 2007-2012 microchip technology inc. 30.1 dc characteristics table 30-1: operating mips vs. voltage characteristic v dd range (in volts) temp range (in c) max mips dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 3.0-3.6v (1) -40c to +85c 40 3.0-3.6v (1) -40c to +125c 40 note 1: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. refer to parameter bo10 in table 30-11 for the minimum and maximum bor values. table 30-2: thermal operating conditions rating symbol min typ max unit industrial temperature devices operating junction temperature range t j -40 +125 c operating ambient temperature range t a -40 +85 c extended temperature devices operating junction temperature range t j -40 +155 c operating ambient temperature range t a -40 +125 c power dissipation: internal chip power dissipation: p int = v dd x (i dd C i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd C v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j C t a )/ ja w table 30-3: thermal packaging characteristics characteristic symbol typ max unit note package thermal resi stance, 44-pin qfn ja 30 c/w 1 package thermal resi stance, 44-pin tfqp ja 40 c/w 1 package thermal resi stance, 28-pin spdip ja 45 c/w 1 package thermal resistance, 28-pin soic ja 50 c/w 1 package thermal resist ance, 28-pin qfn-s ja 30 c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ja ) numbers are achieved by package simulations. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 339 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions operating voltage dc10 supply voltage v dd 3.0 3.6 v industrial and extended dc12 v dr ram data retention voltage (2) 1.8 v dc16 v por v dd start voltage to ensure internal power-on reset signal v ss v dc17 s vdd v dd rise rate to ensure internal power-on reset signal 0.03 v/ms 0-3.0v in 0.1s note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: this is the limit to which v dd can be lowered without losing ram data. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 340 ? 2007-2012 microchip technology inc. table 30-5: dc characteristics: operating current (i dd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions operating current (i dd ) (1) dc20d 18 21 ma -40c 3.3v 10 mips dc20a 18 22 ma +25c dc20b 18 22 ma +85c dc20c 18 25 ma +125c dc21d 30 35 ma -40c 3.3v 16 mips dc21a 30 34 ma +25c dc21b 30 34 ma +85c dc21c 30 36 ma +125c dc22d 34 42 ma -40c 3.3v 20 mips dc22a 34 41 ma +25c dc22b 34 42 ma +85c dc22c 35 44 ma +125c dc23d 49 58 ma -40c 3.3v 30 mips dc23a 49 57 ma +25c dc23b 49 57 ma +85c dc23c 49 60 ma +125c dc24d 63 75 ma -40c 3.3v 40 mips dc24a 63 74 ma +25c dc24b 63 74 ma +85c dc24c 63 76 ma +125c note 1: i dd is primarily a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code exec ution pattern and temperatur e, also have an impact on the current consumption. t he test conditions for all i dd measurements are as follows: oscillator is configured in ec mo de, no pll until 10 mips, osc1 is dr iven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled cpu, sram, program memory and data memory are operational no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero) cpu executing while(1) statement jtag is disabled 2: data in typ column is at 3.3v, +25oc unless otherwise stated. 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 341 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions idle current (i idle ): core off clock on base current (1) dc40d 8 10 ma -40c 3.3v 10 mips dc40a 8 10 ma +25c dc40b 9 10 ma +85c dc40c 10 13 ma +125c dc41d 13 15 ma -40c 3.3v 16 mips dc41a 13 ma +25c 15 dc41b 13 16 ma +85c dc41c 13 19 ma +125c dc42d 15 18 ma -40c 3.3v 20 mips dc42a 16 18 ma +25c dc42b 16 19 ma +85c dc42c 17 22 ma +125c dc43a 23 27 ma +25c 3.3v 30 mips 23 26 dc43d ma -40c dc43b 24 28 ma +85c dc43c 25 31 ma +125c dc44d 31 42 ma -40c 3.3v 40 mips dc44a 31 36 ma +25c dc44b 32 39 ma +85c dc44c 34 43 ma +125c note 1: base i idle current is measured as follows: cpu core is off (i.e., idle mode), oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word external secondary oscillator disabled (i.e., sosco and sosci pins configured as digital i/o inputs) all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled no peripheral modules are operating; however, ever y peripheral is being clocked (defined pmdx bits are set to zero) jtag is disabled 2: data in typ column is at 3.3v, +25oc unless otherwise stated. 3: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 342 ? 2007-2012 microchip technology inc. table 30-7: dc characteristics: power-down current (i pd ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. (3) typical (2) max units conditions power-down current (i pd ) (1) dc60d 24 68 a -40c 3.3v base power-down current (3,4) dc60a 28 87 a+ 2 5 c dc60b 124 292 a+ 8 5 c dc60c 350 1000 a +125c dc61d 8 13 a -40c 3.3v watchdog timer current: i wdt (3,5) dc61a 10 15 a+ 2 5 c dc61b 12 20 a+ 8 5 c dc61c 13 25 a +125c note 1: i pd (sleep) current is measured as follows: cpu core is off (i.e., sleep mode), oscillator is configured in ec mode and external clock active, osc1 is driven with external square wave from rail-to-rail (ec clock overshoot/undershoot < 250 mv required) clko is configured as an i/o input pin in the configuration word all i/o pins are configured as inputs and pulled to v ss mclr = v dd , wdt and fscm are disabled, all peripheral modules are disabled (pmdx bits are all 1 s) rtcc is disabled jtag is disabled 2: data in the typ column is at 3.3v, +25oc unless otherwise stated. 3: the watchdog timer current is the additional current consumed when the wdt module is enabled. this current should be added to the base i pd current. 4: these currents are measured on the device c ontaining the most memory in this family. 5: these parameters are characterized, but are not tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 343 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-8: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended parameter no. typical (1) max doze ratio units conditions dc73a 20 50 1:2 ma -40c 3.3v 40 mips dc73f 17 30 1:64 ma dc73g 17 30 1:128 ma dc70a 20 50 1:2 ma +25c 3.3v 40 mips dc70f 17 30 1:64 ma dc70g 17 30 1:128 ma dc71a 20 50 1:2 ma +85c 3.3v 40 mips dc71f 17 30 1:64 ma dc71g 17 30 1:128 ma dc72a 21 50 1:2 ma +125c 3.3v 40 mips dc72f 18 30 1:64 ma dc72g 18 30 1:128 ma note 1: data in the typical column is at 3.3v, 25c unless otherwise stated. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 344 ? 2007-2012 microchip technology inc. table 30-9: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions v il input low voltage di10 i/o pins v ss 0 . 2v dd v di11 pmp pins v ss 0.15v dd vpmpttl = 1 di15 mclr v ss 0.2 v dd v di16 i/o pins with osc1 or sosci v ss 0 . 2v dd v di18 i/o pins with sdax, sclx v ss 0.3 v dd v smbus disabled di19 i/o pins with sdax, sclx v ss 0.8 v dd v smbus enabled v ih input high voltage di20 di21 i/o pins not 5v tolerant (4) i/o pins 5v tolerant (4) i/o pins not 5v tolerant with pmp (4) i/o pins 5v tolerant with pmp (4) 0.7 v dd 0.7 v dd 0.24 v dd + 0.8 0.24 v dd + 0.8 v dd 5.5 v dd 5.5 vv v v di28 sdax, sclx 0.7 v dd 5.5 v smbus disabled di29 sdax, sclx 2.1 5.5 v smbus enabled i cnpu cnx pull-up current di30 50 250 400 av dd = 3.3v, v pin = v ss note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any positiv e input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical absolute instantaneous sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 345 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 i il input leakage current (2,3) di50 i/o pins 5v tolerant (4) 2 av ss v pin v dd , pin at high-impedance di51 i/o pins not 5v tolerant (4) (excluding an9 through an12) 1 av ss v pin v dd , pin at high-impedance, 40c t a +85c di51a i/o pins not 5v tolerant (4) 2 a shared with external reference pins, 40c t a +85c di51b i/o pins not 5v tolerant (4) (excluding an9 through an12) 3 . 5 av ss v pin v dd , pin at high-impedance, -40c t a +125c di51c i/o pins not 5v tolerant (4) 8 a analog pins shared with external reference pins, -40c t a +125c di51d an9 through an12 11 av ss v pin v dd , pin at high-impedance, -40c t a +85c di51e an9 through an12 13 av ss v pin v dd , pin at high-impedance, -40c t a +125c di55 mclr 2 av ss v pin v dd di56 osc1 2 av ss v pin v dd , xt and hs modes table 30-9: dc characteristics: i/o pi n input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher l eakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any positiv e input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical absolute instantaneous sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 346 ? 2007-2012 microchip technology inc. i icl input low injection current di60a 0 -5 (5,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco, and rb14 i ich input high injection current di60b 0 +5 (6,7,8) ma all pins except v dd , v ss , av dd , av ss , mclr , v cap , sosci, sosco, rb14, and digital 5v-tol- erant designated pins i ict total input injection current di60c (sum of all i/o and control pins) -20 (9) + 2 0 (9) ma absolute instantaneous sum of all input injection currents from all i/o pins (| i icl + | i ich |) i ict table 30-9: dc characteristics: i/o pin input specifications (continued) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current can be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: see the pin diagrams section for the 5v tolerant i/o pins. 5: v il source < (v ss C 0.3). characterized but not tested. 6: non-5v tolerant pins v ih source > (v dd + 0.3), 5v tolerant pins v ih source > 5.5v. characterized but not tested. 7: digital 5v tolerant pins cannot tolerate any positiv e input injection current from input sources > 5.5v. 8: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. 9: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the mathematical absolute instantaneous sum of the input injection currents from all pins do not exceed the specified limit. characterized but not tested. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 347 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-10: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 2x sink driver pins - ra2, ra7- ra10, rb10, rb11, rb7, rb4, rc3-rc9 0 . 4v i ol 3 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 4x sink driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 0 . 4v i ol 6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 8x sink driver pins - ra3, ra4 0 . 4v i ol 10 ma, v dd = 3.3v see note 1 do20 v oh output high voltage i/o pins: 2x source driver pins - ra2, ra7-ra10, rb4, rb7, rb10, rb11, rc3-rc9 2.4 v i oh -3 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 4x source driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 2.4 v i oh -6 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins - ra4, ra3 2.4 v i oh -10 ma, v dd = 3.3v see note 1 do20a v oh 1 output high voltage i/o pins: 2x source driver pins - ra2, ra7-ra10, rb4, rb7, rb10, rb11, rc3-rc9 1.5 v i oh -6 ma, v dd = 3.3v see note 1 2.0 i oh -5 ma, v dd = 3.3v see note 1 3.0 i oh -2 ma, v dd = 3.3v see note 1 output high voltage 4x source driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 1.5 v i oh -12 ma, v dd = 3.3v see note 1 2.0 i oh -11 ma, v dd = 3.3v see note 1 3.0 i oh -3 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins - ra3, ra4 1.5 v i oh -16 ma, v dd = 3.3v see note 1 2.0 i oh -12 ma, v dd = 3.3v see note 1 3.0 i oh -4 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 348 ? 2007-2012 microchip technology inc. table 30-13: internal voltage regulator specifications table 30-11: electrical characteristics: bor dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min (1) typ max (1) units conditions bo10 v bor bor event on v dd transition high-to-low 2.40 2.55 v v dd note 1: parameters are for design guidance only and are not tested in manufacturing. table 30-12: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions program flash memory d130a e p cell endurance 10,000 e/w -40 c to +125 c d131 v pr v dd for read v min 3 . 6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min 3 . 6vv min = minimum operating voltage d134 t retd characteristic retention 20 year p rovided no other specifications are violated d135 i ddp supply current during programming 1 0 m a d136a t rw row write time 1.32 1.74 ms t rw = 11064 frc cycles, t a = +85c, see note 2 d136b t rw row write time 1.28 1.79 ms t rw = 11064 frc cycles, t a = +125c, see note 2 d137a t pe page erase time 20.1 26.5 ms t pe = 168517 frc cycles, t a = +85c, see note 2 d137b t pe page erase time 19.5 27.3 ms t pe = 168517 frc cycles, t a = +125c, see note 2 d138a t ww word write cycle time 42.3 55.9 s t ww = 355 frc cycles, t a = +85c, see note 2 d138b t ww word write cycle time 41.1 57.6 s t ww = 355 frc cycles, t a = +125c, see note 2 note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: other conditions: frc = 7.37 mhz, tun<5:0> = b'011111 (for min), tun<5:0> = b'100000 (for max). this parameter depends on the frc accuracy (see table 30-19 ) and the value of the frc oscillator tuning register (see register 9-4 ). for complete details on calculating the minimum and maximum time see section 5.3 programming operations . standard operating conditions (unless otherwise stated): operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristics min typ max units comments c efc external filter capacitor value (1) 4.7 10 f capacitor must be low series resistance (< 5 ohms) note 1: typical v cap voltage = 2.5v when v dd v ddmin . downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 349 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 30.2 ac characteristics and timing parameters this section defines dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/ x04 ac characteristics and timing parameters. table 30-14: temperature and voltage specifications C ac figure 30-1: load conditions for device timing specifications table 30-15: capacitive loading requirements on output pins ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in ta b l e 3 0 - 1 . param no. symbol characteristic min typ max units conditions do50 c osco osc2/sosco pin 15 pf in xt and hs modes when external clock is used to drive osc1 do56 c io all i/o pins and osc2 50 pf ec mode do58 c b sclx, sdax 400 pf in i 2 c? mode v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 C for all pins except osc2 load condition 2 C for osc2 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 350 ? 2007-2012 microchip technology inc. figure 30-2: external clock timing q1 q2 q3 q4 osc1 clko q1 q2 q3 q4 os20 os25 os30 os30 os40 os41 os31 os31 table 30-16: external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os10 f in external clki frequency (external clocks allowed only in ec and ecpll modes) dc 40 mhz ec oscillator crystal frequency 3.5 10 3.5 1040 33 10 mhzmhz khz mhz xths sosc aux_osc_f in os20 t osc t osc = 1/f osc 12.5 dc ns os25 t cy instruction cycle time (2) 25 dc ns os30 tosl, to s h external clock in (osc1) high or low time 0.375 x t osc 0.625 x t osc ns ec os31 tosr, to s f external clock in (osc1) rise or fall time 2 0n s e c os40 tckr clko rise time (3) 5 . 2n s os41 tckf clko fall time (3) 5 . 2n s os42 g m external oscillator transconductance (4) 14 16 18 ma/v v dd = 3.3v t a = +25oc note 1: data in typ column is at 3.3v, 25c unless otherwise stated. 2: instruction cycle period (t cy ) equals two times the input oscillator ti me-base period. all specified values are based on characterization data fo r that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at min. values with an external clock applied to the osc1/clki pin. when an external clock input is used, the max. cycle time limit is dc (no clock) for all devices. 3: measurements are taken in ec mode. the clko signal is measured on the osc2 pin. 4: data for this parameter is preliminary. this paramete r is characterized, but not tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 351 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-17: pll clock timing specifications (v dd = 3.0v to 3.6v) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions os50 f plli pll voltage controlled oscillator (vco) input frequency range 0.8 8 mhz ecpll, hspll, xtpll modes os51 f sys on-chip vco system frequency 100 200 mhz os52 t lock pll start-up time (lock time) 0.9 1.5 3.1 ms os53 d clk clko stability (jitter) (2) -3 0.5 3 % measured over 100 ms period note 1: data in typ column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 2: these parameters are characterized by similarity, but ar e not tested in manufacturin g. this specification is based on clock cycle by clock cycle meas urements. to calculate the effectiv e jitter for indi vidual time bases or communication clocks use this formula: peripheral clock jitter d clk f osc peripheral bit rate clock -------------------------------------------------------------- ?? ?? ----------------------------------------------------------------------- - = for example: fosc = 32 mhz, d clk = 3%, spi bit rate clock, (i.e., sck) is 2 mhz. spi sck jitter d clk 32 mhz 2 mhz -------------------- ?? ?? ------------------------------ 3% 16 --------- - 3% 4 ------- - 0.75% == = = table 30-18: ac characteristics: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions internal frc accuracy @ 7.3728 mhz (1) f20a frc -2 +2 % -40c t a +85c v dd = 3.0-3.6v f20b frc -5 +5 % -40c t a +125c v dd = 3.0-3.6v note 1: frequency calibrated at 25c and 3.3v. tun bits can be used to compensate for temperature drift. table 30-19: internal rc accuracy ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min typ max units conditions lprc @ 32.768 khz (1) f21a lprc -20 6 +20 % -40c t a +85c v dd = 3.0-3.6v f21b lprc -30 +30 % -40c t a +125c v dd = 3.0-3.6v note 1: change of lprc frequency as v dd changes. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 352 ? 2007-2012 microchip technology inc. figure 30-3: clko and i/o timing characteristics table 30-20: i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ (1) max units conditions do31 t io r port output rise time 10 25 ns do32 t io f port output fall time 10 25 ns di35 t inp intx pin high or low time (input) 20 ns di40 t rbp cnx high or low time (input) 2 t cy note 1: data in typ column is at 3.3v, 25c unless otherwise stated. note: refer to figure 30-1 for load conditions. i/o pin (input) i/o pin (output) di35 old value new value di40 do31 do32 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 353 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-4: reset, watchdog timer, oscillator start-up timer and power-up timer timing characteristics v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset sy11 sy10 sy20 sy13 i/o pins sy13 note: refer to figure 30-1 for load conditions. fscm delay sy35 sy30 sy12 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 354 ? 2007-2012 microchip technology inc. table 30-21: reset, watchdog timer, osci llator start-up timer, power-up timer timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sy10 t mc lm c l r pulse width (low) 2 s -40c to +85c sy11 t pwrt power-up timer period 2 48 1632 64 128 ms -40c to +85c user programmable sy12 t por power-on reset delay 3 10 30 s -40c to +85c sy13 t ioz i/o high-impedance from mclr low or watchdog timer reset 0.68 0.72 1.2 s sy20 t wdt 1 watchdog timer time-out period s e e section 27.4 watchdog timer (wdt) and lprc specification f21 ( table 30-19 ) sy30 t ost oscillator start-up timer period 1024t osc t osc = osc1 period sy35 t fscm fail-safe clock monitor delay 500 900 s -40c to +85c note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 355 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-5: timer1, 2, 3 and 4 external clock timing characteristics table 30-22: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions ta10 t tx h txck high time synchronous, no prescaler t cy + 20 ns must also meet parameter ta15. n = prescale value (1, 8, 64, 256) synchronous, with prescaler (t cy + 20)/n ns asynchronous 20 ns ta11 t tx l txck low time synchronous, no prescaler (t cy + 20) ns must also meet parameter ta15. n = prescale value (1, 8, 64, 256) synchronous, with prescaler (t cy + 20)/n ns asynchronous 20 ns ta15 t tx p txck input period synchronous, no prescaler 2 t cy + 40 ns synchronous, with prescaler greater of: 40 ns or (2 t cy + 40)/ n n = prescale value (1, 8, 64, 256) asynchronous 40 ns os60 ft1 sosci/t1ck oscillator input frequency range (oscillator enabled by setting bit tcs (t1con<1>)) dc 50 khz ta20 t ckextmrl delay from external txck clock edge to timer increment 0.75 t cy + 40 1.75 t cy + 40 note 1: timer1 is a type a. note: refer to figure 30-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 356 ? 2007-2012 microchip technology inc. table 30-23: timer2 and timer 4 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tb10 ttxh txck high time synchronous mode greater of: 20 or (t cy + 20)/n n s must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb11 ttxl txck low time synchronous mode greater of: 20 or (t cy + 20)/n ns must also meet parameter tb15 n = prescale value (1, 8, 64, 256) tb15 ttxp txck input period synchronous mode greater of: 40 or (2 t cy + 40)/n ns n = prescale value (1, 8, 64, 256) tb20 t ckextmrl delay from external txck clock edge to timer incre- ment 0.75 t cy + 40 1.75 t cy + 40 ns note 1: these parameters are characterized, but are not tested in manufacturing. table 30-24: timer3 and timer5 external clock timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions tc10 ttxh txck high time synchronous t cy + 20 ns must also meet parameter tc15 tc11 ttxl txck low time synchronous t cy + 20 ns must also meet parameter tc15 tc15 ttxp txck input period synchronous, with prescaler 2 t cy + 40 ns n = prescale value (1, 8, 64, 256) tc20 t ckextmrl delay from external txck clock edge to timer incre- ment 0.75 t cy + 40 1.75 t cy + 40 ns note 1: these parameters are characterized, but are not tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 357 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-6: input capture (capx) timing characteristics figure 30-7: output compare module (ocx) timing characteristics table 30-25: input capture timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min max units conditions ic10 tccl icx input low time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic11 tcch icx input high time no prescaler 0.5 t cy + 20 ns with prescaler 10 ns ic15 tccp icx input period (t cy + 40)/n ns n = prescale value (1, 4, 16) note 1: these parameters are characterized but not tested in manufacturing. table 30-26: output compare module timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc10 tccf ocx output fall time ns see parameter d032 oc11 tccr ocx output rise time ns see parameter d031 note 1: these parameters are characterized but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 30-1 for load conditions. ocx oc11 oc10 (output compare note: refer to figure 30-1 for load conditions. or pwm mode) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 358 ? 2007-2012 microchip technology inc. figure 30-8: oc/pwm module ti ming characteristics table 30-27: simple oc/pwm mode timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ max units conditions oc15 t fd fault input to pwm i/o change t cy + 20 ns oc20 t flt fault input pulse-width t cy + 20 ns note 1: these parameters are characterized but not tested in manufacturing. ocfa ocx oc20 oc15 active tri-state downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 359 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-28: spix maximum data/clock rate summary figure 30-9: spix master mode (ha lf-duplex, transmit only cke = 0 ) timing characteristics figure 30-10: spix master mode (h alf-duplex, transmit only cke = 1 ) timing characteristics ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended maximum data rate master transmit only (half-duplex) master transmit/receive (full-duplex) slave transmit/receive (full-duplex) cke ckp smp 15 mhz table 30-29 0 , 10 , 10 , 1 9 mhz table 30-30 10 , 11 9 mhz table 30-31 00 , 11 15 mhz table 30-32 100 11 mhz table 30-33 110 15 mhz table 30-34 010 11 mhz table 30-35 000 sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 30-1 for load conditions. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 30-1 for load conditions. sp36 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 360 ? 2007-2012 microchip technology inc. table 30-29: spix master mode (half-duplex, transmit only) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency 15 mhz see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdiv2sch, tdiv2scl sdox data output setup to first sckx edge 30 ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. theref ore, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 361 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-11: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing characteristics table 30-30: spix master mode (full-duplex, cke = 1 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency 9 mhz see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sp10 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 sp30, sp31 note: refer to figure 30-1 for load conditions. sp36 sp41 msb in lsb in bit 14 - - - -1 sdix sp40 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 362 ? 2007-2012 microchip technology inc. figure 30-12: spix master mode (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing characteristics table 30-31: spix master mo de (full-duplex, cke = 0 , ckp = x , smp = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp10 tscp maximum sck frequency 9 mhz -40oc to +125oc and see note 3 sp20 tscf sckx output fall time ns see parameter do32 and note 4 sp21 tscr sckx output rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 6 20 ns sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 111 ns. the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30, sp31 sp30, sp31 note: refer to figure 30-1 for load conditions. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 363 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-13: spix slave mode (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 30-1 for load conditions. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 364 ? 2007-2012 microchip technology inc. table 30-32: spix slave mo de (full-duplex, cke = 1 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency 15 mhz see note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ns sp51 tssh2doz ssx to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge 5 0n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 365 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-14: spix slave mode (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp50 sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp35 sp52 sp52 sp73 sp72 sp72 sp73 sp70 sp40 sp41 note: refer to figure 30-1 for load conditions. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 366 ? 2007-2012 microchip technology inc. table 30-33: spix slave mo de (full-duplex, cke = 1 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency 11 mhz see note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ns sp51 tssh2doz ssx to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ns see note 4 sp60 tssl2dov sdox data output valid after ssx edge 5 0n s note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 367 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-15: spix slave mode (full-duplex cke = 0 , ckp = 1 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 30-1 for load conditions. sdi x downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 368 ? 2007-2012 microchip technology inc. table 30-34: spix slave mo de (full-duplex, cke = 0 , ckp = 1 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency 15 mhz see note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ns sp51 tssh2doz ssx to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 66.7 ns. ther efore, the sck clock gener ated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 369 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-16: spix slave mode (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp70 note: refer to figure 30-1 for load conditions. sdi x downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 370 ? 2007-2012 microchip technology inc. table 30-35: spix slave mo de (full-duplex, cke = 0 , ckp = 0 , smp = 0 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions sp70 tscp maximum sck input frequency 11 mhz see note 3 sp72 tscf sckx input fall time ns see parameter do32 and note 4 sp73 tscr sckx input rise time ns see parameter do31 and note 4 sp30 tdof sdox data output fall time ns see parameter do32 and note 4 sp31 tdor sdox data output rise time ns see parameter do31 and note 4 sp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 62 0n s sp36 tdov2sch, tdov2scl sdox data output setup to first sckx edge 30 ns sp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 30 ns sp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 30 ns sp50 tssl2sch, tssl2scl ssx to sckx or sckx input 120 ns sp51 tssh2doz ssx to sdox output high-impedance (4) 10 50 ns sp52 tsch2ssh tscl2ssh ssx after sckx edge 1.5 t cy + 40 ns see note 4 note 1: these parameters are characterized, but are not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. 3: the minimum clock period for sckx is 91 ns. therefor e, the sck clock generated by the master must not violate this specification. 4: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 371 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-17: i2cx bus start/stop bits timing characteristics (master mode) figure 30-18: i2cx bus data timing characteristics (master mode) im31 im34 sclx sdax start condition stop condition im30 im33 note: refer to figure 30-1 for load conditions. im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 30-1 for load conditions. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 372 ? 2007-2012 microchip technology inc. table 30-36: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min (1) max units conditions im10 t lo : scl clock low time 100 khz mode t cy /2 (brg + 1) s 400 khz mode t cy /2 (brg + 1) s 1 mhz mode (2) t cy /2 (brg + 1) s im11 t hi : scl clock high time 100 khz mode t cy /2 (brg + 1) s 400 khz mode t cy /2 (brg + 1) s 1 mhz mode (2) t cy /2 (brg + 1) s im20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) 100 ns im21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (2) 300 ns im25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode (2) 40 ns im26 t hd : dat data input hold time 100 khz mode 0 s 400 khz mode 0 0.9 s 1 mhz mode (2) 0.2 s im30 t su : sta start condition setup time 100 khz mode t cy /2 (brg + 1) s only relevant for repeated start condition 400 khz mode t cy /2 (brg + 1) s 1 mhz mode (2) t cy /2 (brg + 1) s im31 t hd : sta start condition hold time 100 khz mode t cy /2 (brg + 1) s after this period the first clock pulse is generated 400 khz mode t cy /2 (brg + 1) s 1 mhz mode (2) t cy /2 (brg + 1) s im33 t su : sto stop condition setup time 100 khz mode t cy /2 (brg + 1) s 400 khz mode t cy /2 (brg + 1) s 1 mhz mode (2) t cy /2 (brg + 1) s im34 t hd : sto stop condition 100 khz mode t cy /2 (brg + 1) ns hold time 400 khz mode t cy /2 (brg + 1) ns 1 mhz mode (2) t cy /2 (brg + 1) ns im40 t aa : scl output valid from clock 100 khz mode 3500 ns 400 khz mode 1000 ns 1 mhz mode (2) 400 ns im45 t bf : sda bus free time 100 khz mode 4.7 s time the bus must be free before a new transmission can start 400 khz mode 1.3 s 1 mhz mode (2) 0.5 s im50 c b bus capacitive loading 400 pf im51 t pgd pulse gobbler delay 65 390 ns see note 3 note 1: brg is the value of the i 2 c baud rate generator. refer to section 19. inter-integrated circuit? (i 2 c?) (ds70195) in the dspic33f/pic24h family reference manual. please see the microchip website ( www.microchip.com ) for the latest dspic33f/pic24h family reference manual chapters. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: typical value for this parameter is 130 ns. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 373 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-19: i2cx bus start/stop bits timing characteristics (slave mode) figure 30-20: i2cx bus data timing characteristics (slave mode) is31 is34 sclx sdax start condition stop condition is30 is33 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclxsdax in sdax out downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 374 ? 2007-2012 microchip technology inc. table 30-37: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param. symbol characteristic min max units conditions is10 t lo : scl clock low time 100 khz mode 4.7 s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 s is11 t hi : scl clock high time 100 khz mode 4.0 s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 s device must operate at a minimum of 10 mhz 1 mhz mode (1) 0.5 s is20 t f : scl sdax and sclx fall time 100 khz mode 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) 100 ns is21 t r : scl sdax and sclx rise time 100 khz mode 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) 300 ns is25 t su : dat data input setup time 100 khz mode 250 ns 400 khz mode 100 ns 1 mhz mode (1) 100 ns is26 t hd : dat data input hold time 100 khz mode 0 s 400 khz mode 0 0.9 s 1 mhz mode (1) 00 . 3 s is30 t su : sta start condition setup time 100 khz mode 4.7 s only relevant for repeated start condition 400 khz mode 0.6 s 1 mhz mode (1) 0.25 s is31 t hd : sta start condition hold time 100 khz mode 4.0 s after this period, the first clock pulse is generated 400 khz mode 0.6 s 1 mhz mode (1) 0.25 s is33 t su : sto stop condition setup time 100 khz mode 4.7 s 400 khz mode 0.6 s 1 mhz mode (1) 0.6 s is34 t hd : st o stop condition hold time 100 khz mode 4000 ns 400 khz mode 600 ns 1 mhz mode (1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns 400 khz mode 0 1000 ns 1 mhz mode (1) 0 350 ns is45 t bf : sda bus free time 100 khz mode 4.7 s time the bus must be free before a new transmission can start 400 khz mode 1.3 s 1 mhz mode (1) 0.5 s is50 c b bus capacitive loading 400 pf note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 375 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-21: dci module (multi-channel, i 2 s modes) timing characteristics cofs csck (scke = 0 ) csck (scke = 1 ) csdo csdi cs11 cs10 cs40 cs41 cs21 cs20 cs35 cs21 msb lsb msb in lsb in cs31 high-z high-z 70 cs30 cs51 cs50 cs55 note: refer to figure 30-1 for load conditions. cs20 cs56 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 376 ? 2007-2012 microchip technology inc. table 30-38: dci module (multi-channel, i 2 s modes) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions cs10 t csckl csck input low time (csck pin is an input) t cy /2 + 20 ns csck output low time (3) (csck pin is an output) 30 ns cs11 t csckh csck input high time (csck pin is an input) t cy /2 + 20 ns csck output high time (3) (csck pin is an output) 30 ns cs20 t csckf csck output fall time (4) (csck pin is an output) 1 02 5n s cs21 t csckr csck output rise time (4) (csck pin is an output) 1 02 5n s cs30 t csdof csdo data output fall time (4) 1 02 5n s cs31 t csdor csdo data output rise time (4) 1 02 5n s cs35 t dv clock edge to csdo data valid 10 ns cs36 t div clock edge to csdo tri-stated 10 20 ns cs40 t csdi setup time of csdi data input to csck edge (csck pin is input or output) 20 ns cs41 t hcsdi hold time of csdi data input to csck edge (csck pin is input or output) 20 ns cs50 t cofsf cofs fall time (cofs pin is output) 1 02 5n ss e e note 1 cs51 t cofsr cofs rise time (cofs pin is output) 1 02 5n ss e e note 1 cs55 t scofs setup time of cofs data input to csck edge (cofs pin is input) 20 ns cs56 t hcofs hold time of cofs data input to csck edge (cofs pin is input) 20 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for csck is 100 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all dci pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 377 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-22: dci module (ac-link mode) timing characteristics sync bit_clk sdox sdix cs61 cs60 cs65 cs66 cs80 cs21 msb in cs75 lsb cs76 (cofs) (csck) lsb msb cs72 cs71 cs70 cs76 cs75 (csdo) (csdi) cs62 cs20 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 378 ? 2007-2012 microchip technology inc. table 30-39: dci module (ac-li nk mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1,2) min typ (3) max units conditions cs60 t bclkl bit_clk low time 36 40.7 45 ns cs61 t bclkh bit_clk high time 36 40.7 45 ns cs62 t bclk bit_clk period 81.4 ns bit clock is input cs65 t sacl input setup time to falling edge of bit_clk 1 0 n s cs66 t hacl input hold time from falling edge of bit_clk 1 0 n s cs70 t synclo sync data output low time 19.5 ssee note 1 cs71 t synchi sync data output high time 1.3 ssee note 1 cs72 t sync sync data output period 20.8 ssee note 1 cs75 t racl rise time, sync, sdata_out 30 ns c load = 50 pf, v dd = 3v cs76 t facl fall time, sync, sdata_out 30 ns c load = 50 pf, v dd = 3v cs80 t ovdacl output valid delay from rising edge of bit_clk 1 5 n s note 1: these parameters are characterized but not tested in manufacturing. 2: these values assume bit_clk frequency is 12.288 mhz. 3: data in typ column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 379 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-23: ecan? module i/o timing characteristics table 30-40: ecan? module i/o timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic (1) min typ (2) max units conditions ca10 tiof port output fall time ns see parameter d032 ca11 tior port output rise time ns see parameter d031 ca20 tcwf pulse-width to trigger can wake-up filter 120 ns note 1: these parameters are characterized but not tested in manufacturing. 2: data in typ column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. citx pin (output) ca10 ca11 old value new value ca20 cirx pin (input) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 380 ? 2007-2012 microchip technology inc. table 30-41: adc module specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions device supply ad01 av dd module v dd supply greater of v dd C 0.3 or 3.0 lesser of v dd + 0.3 or 3.6 v ad02 av ss module v ss supply v ss C 0.3 v ss + 0.3 v reference inputs ad05 v refh reference voltage high av ss + 2.5 av dd v ad05a 3.0 3.6 v v refh = av dd v refl = av ss = 0 ad06 v refl reference voltage low av ss av dd C 2.5 v ad06a 0 0 v v refh = av dd v refl = av ss = 0 ad07 v ref absolute reference voltage 2.5 3.6 v v ref = v refh - v refl ad08 i ref current drain 10 a adc off ad09 i ad operating current 7.02.7 9.0 3.2 mama adc operating in 10-bit mode, see note 1 adc operating in 12-bit mode, see note 1 analog input ad12 v inh input voltage range v inh v inl v refh v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), positive input ad13 v inl input voltage range v inl v refl av ss + 1v v this voltage reflects sample and hold channels 0, 1, 2, and 3 (ch0-ch3), negative input ad17 r in recommended imped- ance of analog voltage source 200200 ? 10-bit adc 12-bit adc note 1: these parameters are not characterized or tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 381 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-42: adc module specifications (12-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (12-bit mode) C measurements with external v ref +/v ref - ad20a nr resolution (1) 12 data bits bits ad21a inl integral nonlinearity -2 +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22a dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23a g err gain error 3.4 10 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24a e off offset error 0.9 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25a monotonicity guaranteed adc accuracy (12-bit mode) C measurements with internal v ref +/v ref - ad20a nr resolution (1) 12 data bits bits ad21a inl integral nonlinearity -2 +2 lsb v inl = av ss = 0v, av dd = 3.6v ad22a dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = 0v, av dd = 3.6v ad23a g err gain error 2 10.5 20 lsb v inl = av ss = 0v, av dd = 3.6v ad24a e off offset error 2 3.8 10 lsb v inl = av ss = 0v, av dd = 3.6v ad25a monotonicity guaranteed dynamic performance (12-bit mode) ad30a thd total harmonic distortion -75 db ad31a sinad signal to noise and distortion 68.5 69.5 db ad32a sfdr spurious free dynamic range 80 db ad33a f nyq input signal bandwidth 250 khz ad34a enob effective number of bits 11.09 11.3 bits note 1: injection currents > |0| can affect the adc results by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3v) or v il source < (v ss C 0.3v). downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 382 ? 2007-2012 microchip technology inc. table 30-43: adc module specifications (10-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions adc accuracy (10-bit mode) C measurements with external v ref +/v ref - ad20b nr resolution (1) 10 data bits bits ad21b inl integral nonlinearity -1.5 +1.5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad22b dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad23b g err gain error 3 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad24b e off offset error 2 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v ad25b monotonicity guaranteed adc accuracy (10-bit mode) C measurements with internal v ref +/v ref - ad20b nr resolution (1) 10 data bits bits ad21b inl integral nonlinearity -1 +1 lsb v inl = av ss = 0v, av dd = 3.6v ad22b dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = 0v, av dd = 3.6v ad23b g err gain error 3 7 15 lsb v inl = av ss = 0v, av dd = 3.6v ad24b e off offset error 1.5 3 7 lsb v inl = av ss = 0v, av dd = 3.6v ad25b monotonicity guaranteed dynamic performance (10-bit mode) ad30b thd total harmonic distortion -64 db ad31b sinad signal to noise and distortion 57 58.5 db ad32b sfdr spurious free dynamic range 72 db ad33b f nyq input signal bandwidth 550 khz ad34b enob effective number of bits 9.16 9.4 bits note 1: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 383 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-24: adc conversion (12-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 7 1 C software sets ad1con. samp to start sampling. 2 C sampling starts after discharge period. t samp is described in 3 C software clears ad1con. samp to start conversion. 4 C sampling ends, conversion sequence starts. 5 C convert bit 11. 9 C one t ad for end of conversion. ad50 9 6 C convert bit 10. 7 C convert bit 1. 8 C convert bit 0. execution in the dspic33f/pic24h family reference manual . s ection 16. analog-to-digital converter (adc) (ds70183) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 384 ? 2007-2012 microchip technology inc. table 30-44: adc conversion (12- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ (2) max. units conditions clock parameters (1) ad50 t ad adc clock period 117.6 ns ad51 t rc adc internal rc oscillator period 250 ns conversion rate ad55 t conv conversion time 14 t ad ns ad56 f cnv throughput rate 500 ksps ad57 t samp sample time 3 t ad timing parameters ad60 t pcs conversion start from sample trigger (2) 2 t ad 3 t ad auto convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (2) 2 t ad 3 t ad ad62 t css conversion completion to sample start (asam = 1 ) (2) 0.5 t ad ad63 t dpu time to stabilize analog stage from adc off to adc on (2,3) 2 0 s note 1: because the sample caps eventually loses charge, clock rates below 10 kh z may affect linearity performance, especially at elevated temperatures. 2: these parameters are characterized but not tested in manufacturing. 3: the t dpu is the time required for the adc module to stabilize at the appropriate level when the module is turned on adon bit (ad1con1<15>) = 1. during this time, the adc re sult is indeterminate. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 385 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-25: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 0 , ssrc<2:0> = 000 ) figure 30-26: adc conversion (10-bit mode) timing characteristics (chps<1:0> = 01 , simsam = 0 , asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ad60 done ad1if 1 2 3 4 5 6 8 5 6 7 1 C software sets ad1con. samp to start sampling. 2 C sampling starts after discharge period. t samp is described in section 16. analog-to-digital converter (adc) 3 C software clears ad1con. samp to start conversion. 4 C sampling ends, conversion sequence starts. 5 C convert bit 9. 8 C one t ad for end of conversion. ad50 7 ad55 8 6 C convert bit 8. 7 C convert bit 0. execution (ds70183) in the dspic33f/pic24h family reference manual . 1 2 3 4 5 6 4 5 6 8 1 C software sets ad1con. adon to start ad operation. 2 C sampling starts after discharge period. t samp is described in 3 C convert bit 9. 4 C convert bit 8. 5 C convert bit 0. 7 3 6 C one t ad for end of conversion. 7 C begin conversion of next channel. 8 C sample for time specified by samc<4:0>. adclk instruction set adon execution samp t samp ad1if done ad55 ad55 t samp ad55 ad50 section 16. analog-to-digital converter (adc) (ds70183) in the dspic33f/pic24h family reference manual' . downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 386 ? 2007-2012 microchip technology inc. table 30-46: audio dac module specifications table 30-45: adc conversion (10- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ (2) max. units conditions clock parameters (1) ad50 t ad adc clock period 76 ns ad51 t rc adc internal rc oscillator period 250 ns conversion rate ad55 t conv conversion time 12 t ad ad56 f cnv throughput rate 1.1 msps ad57 t samp sample time 2 t ad timing parameters ad60 t pcs conversion start from sample trigger (2) 2 t ad 3 t ad auto-convert trigger not selected ad61 t pss sample start from setting sample (samp) bit (2) 2 t ad 3 t ad ad62 t css conversion completion to sample start (asam = 1 ) (2) 0.5 t ad ad63 t dpu time to stabilize analog stage from adc off to adc on (2,3) 2 0 s note 1: because the sample caps eventually loses charge, clock rates below 10 kh z may affect linearity performance, especially at elevated temperatures. 2: these parameters are characterized but not tested in manufacturing. 3: the t dpu is the time required for the adc module to stabilize at the appropriate level when the module is turned on adon bit (ad1con1<15>) = 1 . during this time, the adc result is indeterminate. ac/dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions clock parameters da01 v od + positive output differential voltage 11 . 1 52 vv od + = v dach C v dacl see note 1, 2 da02 v od - negative output differential voltage -2 -1.15 -1 v v od - = v dacl C v dach see note 1, 2 da03 v res resolution 16 bits da04 g err gain error 3.1 % da08 f dac clock frequency 25.6 mhz da09 f samp sample rate 0 100 khz da10 f input input data frequency 0 45 khz sampling frequency = 100 khz da11 t init initialization period 1024 clks time before first sample da12 snr signal-to-noise ratio 61 db sampling frequency = 96 khz note 1: measured v dach and v dacl output with respect to v ss , with 15 a load and form bit (dac x con<8>) = 0 . 2: this parameter is tested at -40c t a 85c only. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 387 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 30-47: comparator timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions 300 t resp response time (1,2) 150 400 ns 301 t mc 2 ov comparator mode change to output valid (1) 1 0 s note 1: parameters are characterized but not tested. 2: response time measured with one comparator input at (v dd - 1.5)/2, while the other input transitions from v ss to v dd . table 30-48: comparator module specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions d300 v ioff input offset voltage (1) 1 0m v d301 v icm input common mode voltage (1) 0 a vdd -1.5v v d302 cmrr common mode rejection ratio (1) -54 db note 1: parameters are characterized but not tested. table 30-49: comparator reference voltage settling time specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions vr310 t set settling time (1) 1 0 s note 1: settling time measured while cvrr = 1 and cvr3:cvr0 bits transition from 0000 to 1111 . table 30-50: comparator reference voltage specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions vrd310 cv res resolution cv rsrc /24 cv rsrc /32 lsb vrd311 cvr aa absolute accuracy 0.5 lsb vrd312 cvr ur unit resistor value (r) 2k downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 388 ? 2007-2012 microchip technology inc. figure 30-27: parallel slave port timing diagram cs ps3 ps4 ps1 ps2 rd wr pmd<7:0> table 30-51: parallel slave port time specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min. typ max. units conditions ps1 tdtv2wrh data in valid before wr or cs inactive (setup time) 20 ns ps2 twrh2dti wr or cs inactive to data-in invalid (hold time) 20 ns ps3 trdl2dtv rd and cs to active data-out valid 80 ns ps4 trdh2dti rd active or cs inactive to data-out invalid 10 30 ns downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 389 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 30-28: parallel master port read timing diagram p1 p2 p3 p4 p1 p2 p3 p4 p1 p2 system pma<13:8> pmd<7:0> clock pmrd pmall/pmalh pmcs1 address address <7:0> data pm2 pm3 pm6 pm7 pm5 pm1 pmwr table 30-52: parallel master port read timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min. typ max. units conditions pm1 pmall/pmalh pulse-width 0.5 t cy n s pm2 address out valid to pmall/pmalh invalid (address setup time) 0.75 t cy n s pm3 pmall/pmalh invalid to address out invalid (address hold time) 0.25 t cy n s pm5 pmrd pulse-width 0.5 t cy n s pm6 pmrd or pmenb active to data in valid (data setup time) 150 ns pm7 pmrd or pmenb inactive to data in invalid (data hold time) 5n s downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 390 ? 2007-2012 microchip technology inc. figure 30-29: parallel master port write timing diagram table 30-54: dma read/write timing requirements p1 p2 p3 p4 p1 p2 p3 p4 p1 p2 system pma<13:8> pmd<7:0> clock pmwr pmall/pmalh pmcs1 address address <7:0> data pm12 pm13 pm16 data pm11 pmrd table 30-53: parallel master po rt write timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min. typ max. units conditions pm11 pmwr pulse-width 0.5 t cy n s pm12 data out valid befo re pmwr or pmenb goes inactive (data setup time) n s pm13 pmwr or pmemb invalid to data out invalid (data hold time) n s pm16 pmcsx pulse-width t cy - 5 ns ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. characteristic min. typ max. units conditions dm1 dma read/write cycle time 1 t cy ns downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 391 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 31.0 high temperature electrical characteristics this section provides an overview of dspic33fj32g p302/304, dspic33fj64gpx02/x 04, and dspic33fj128gpx02/ x04 electrical characteristics for devices operating in an ambient temperature range of -40c to +150c. the specifications between -40c to + 150c are identical to those shown in section 30.0 electri cal characteristics for operation between -40c to +125c, with the exc eption of the parameters listed in this section. parameters in this section begin with an h, which den otes high temperature. for example, parameter dc10 in section 30.0 electrical characteristics is the industrial and extended temperature equivalent of hdc10. absolute maximum ratings for the dspic33fj32gp302/3 04, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 high temperature devices are listed below. exposure to these maximum rating conditions for extended periods can affect device reliability. functional operation of the device at these or any other condit ions above the parameters indicated in the operation listings of this specification is not implied. absolute maximum ratings (1) ambient temperature under bias (4) .........................................................................................................-40c to +150c storage temperature ............................................................................................................ .................. -65c to +160c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant with respect to v ss (5) .................................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd < 3.0v (5) ....................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd 3.0v (5) .................................................... -0.3v to 5.6v maximum current out of v ss pin ........................................................................................................................... ..60 ma maximum current into v dd pin (2) .............................................................................................................................60 ma maximum junction temperature...... ............................................................................................. .......................... +155c maximum current sourced/sunk by any 2x i/o pin (3) ................................................................................................2 ma maximum current sourced/sunk by any 4x i/o pin (3) ................................................................................................4 ma maximum current sourced/sunk by any 8x i/o pin (3) ................................................................................................8 ma maximum current sunk by all ports combined ........... ......................................................................... ....................70 ma maximum current sourced by all ports combined (2) ................................................................................................70 ma note 1: stresses above those listed under absolute maximu m ratings can cause permanent damage to the device. this is a stress rating only, and functional oper ation of the device at th ose or any other conditions above those indicated in the operation listings of this specification is not impl ied. exposure to maximum rating conditions for extended periods can affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 31-2 ). 3: unlike devices at 125c and below, the specificati ons in this section also apply to the clkout, v ref +, v ref -, sclx, sdax, pgcx, and pgdx pins. 4: aec-q100 reliability testing for devices intended to operate at 150c is 1,000 hours. any design in which the total operating time from 125c to 150c will be greater than 1,000 hours is not warranted without prior written approval from microchip technology inc. 5: refer to the pin diagrams section for 5v tolerant pins. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 392 ? 2007-2012 microchip technology inc. 31.1 high temperature dc characteristics table 31-1: operating mips vs. voltage table 31-2: thermal operating conditions table 31-3: dc temperature and voltage specifications characteristic v dd range (in volts) temperature range (in c) max mips dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 3.0v to 3.6v (1) -40c to +150c 20 note 1: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. rating symbol min typ max unit high temperature devices operating junction temperature range t j -40 +155 c operating ambient temperature range t a -40 +150 c power dissipation: internal chip power dissipation: p int = v dd x (i dd - i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = ({v dd - v oh } x i oh ) + (v ol x i ol ) maximum allowed power dissipation p dmax (t j - t a )/ ja w dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. symbol characteristic min typ max units conditions operating voltage hdc10 supply voltage v dd 3.0 3.3 3.6 v -40c to +150c note 1: device is functional at v bormin < v dd < v ddmin . analog modules such as the adc will have degraded performance. device functionality is tested but not characterized. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 393 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 31-4: dc characteristics: power-down current (i pd ) table 31-5: dc characteristics: doze current (i doze ) dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature parameter no. typical max units conditions power-down current (i pd ) hdc60e 250 2000 a +150c 3.3v base power-down current (1,3) hdc61c 3 5 a +150c 3.3v watchdog timer current: i wdt (2,4) note 1: base i pd is measured with all peripheral s and clocks shut down. all i/os are configured as inputs and pulled to v ss . wdt, etc., are all switched off, and vregs (rcon<8>) = 1 . 2: the current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 3: these currents are measured on the device c ontaining the most memory in this family. 4: these parameters are characterized, but are not tested in manufacturing. dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150oc for high temperature parameter no. typical (1) max doze ratio units conditions hdc72a 39 45 1:2 ma +150c 3.3v 20 mips hdc72f 18 25 1:64 ma hdc72g 18 25 1:128 ma note 1: parameters with doze ratios of 1:2 and 1:64 are c haracterized, but are not tested in manufacturing. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 394 ? 2007-2012 microchip technology inc. table 31-6: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 2x sink driver pins - ra2, ra7- ra10, rb10, rb11, rb7, rb4, rc3-rc9 0 . 4v i ol 1.8 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 4x sink driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 0 . 4v i ol 3.6 ma, v dd = 3.3v see note 1 output low voltage i/o pins: 8x sink driver pins - ra3, ra4 0 . 4v i ol 6 ma, v dd = 3.3v see note 1 do20 v oh output high voltage i/o pins: 2x source driver pins - ra2, ra7-ra10, rb4, rb7, rb10, rb11, rc3-rc9 2.4 v i ol -1.8 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 4x source driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 2.4 v i ol -3 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins - ra4, ra3 2.4 v i ol -6 ma, v dd = 3.3v see note 1 do20a v oh 1 output high voltage i/o pins: 2x source driver pins - ra2, ra7-ra10, rb4, rb7, rb10, rb11, rc3-rc9 1.5 v i oh -1.9 ma, v dd = 3.3v see note 1 2.0 i oh -1.85 ma, v dd = 3.3v see note 1 3.0 i oh -1.4 ma, v dd = 3.3v see note 1 output high voltage 4x source driver pins - ra0, ra1, rb0-rb3, rb5, rb6, rb8, rb9, rb12-rb15, rc0-rc2 1.5 v i oh -3.9 ma, v dd = 3.3v see note 1 2.0 i oh -3.7 ma, v dd = 3.3v see note 1 3.0 i oh -2 ma, v dd = 3.3v see note 1 output high voltage i/o pins: 8x source driver pins - ra3, ra4 1.5 v i oh -7.5 ma, v dd = 3.3v see note 1 2.0 i oh -6.8 ma, v dd = 3.3v see note 1 3.0 i oh -3 ma, v dd = 3.3v see note 1 note 1: parameters are characterized, but not tested. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 395 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 31-7: dc characteristics: program memory dc characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions program flash memory hd130 e p cell endurance 10,000 e/w -40 c to +150oc (2) hd134 t retd characteristic retention 20 year 1000 e/w cycles or less and no other specifications are violated note 1: these parameters are assured by design, but ar e not characterized or tested in manufacturing. 2: programming of the flash memory is allowed up to 150c. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 396 ? 2007-2012 microchip technology inc. 31.2 ac characteristics and timing parameters the information contained in this section defines dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 ac characteristics and timing parameters for high temperature devices. however, all ac timing specifications in this section are the same as those in section 30.2 ac characteristics and timing parameters , with the exception of the parameters listed in this section. parameters in this section begin with an h, which denotes high temperature. for example, parameter os53 in section 30.2 ac characteristics and timing parameters is the industrial and extended temperature equivalent of hos53. table 31-8: temperature and voltage specifications C ac figure 31-1: load conditions for device timing specifications table 31-9: pll clock timing specifications ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature operating voltage v dd range as described in table 31-1 . v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 C for all pins except osc2 load condition 2 C for osc2 ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic mi n typ max units conditions hos53 d clk clko stability (jitter) (1) -5 0.5 5 % measured over 100 ms period note 1: these parameters are characterized, but are not tested in manufacturing. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 397 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 31-10: spix master mode (cke = 0 ) timing requirements table 31-11: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 1 02 5n s hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ns hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 35 ns note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 1 02 5n s hsp36 tdov2sc, tdov2scl sdox data output setup to first sckx edge 35 ns hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 28 ns hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 35 ns note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 398 ? 2007-2012 microchip technology inc. table 31-12: spix module slave mode (cke = 0 ) timing requirements table 31-13: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 3 5n s hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ns hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 25 ns hsp51 tssh2doz ssx to sdox output high-impedance 15 55 ns see note 2 note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic (1) min typ max units conditions hsp35 tsch2dov, tscl2dov sdox data output valid after sckx edge 35 ns hsp40 tdiv2sch, tdiv2scl setup time of sdix data input to sckx edge 25 ns hsp41 tsch2dil, tscl2dil hold time of sdix data input to sckx edge 25 ns hsp51 tssh2doz ssx to sdo x output high-impedance 15 55 ns see note 2 hsp60 tssl2dov sdox data output valid after ssx edge 55 ns note 1: these parameters are characterized but not tested in manufacturing. 2: assumes 50 pf load on all spix pins. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 399 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 31-14: adc module specifications table 31-15: adc module specifications (12-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions reference inputs had08 i ref current drain 250 600 50 a a adc operating, see note 1 adc off, see note 1 note 1: these parameters are not characterized or tested in manufacturing. 2: these parameters are characterized, but are not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions adc accuracy (12-bit mode) C measurements with external v ref +/v ref - (1) had20a nr resolution (3) 12 data bits bits had21a inl integral nonlinearity -2 +2 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had22a dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had23a g err gain error -2 10 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had24a e off offset error -3 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v adc accuracy (12-bit mode) C measurements with internal v ref +/v ref - (1) had20a nr resolution (3) 12 data bits bits had21a inl integral nonlinearity -2 +2 lsb v inl = av ss = 0v, av dd = 3.6v had22a dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = 0v, av dd = 3.6v had23a g err gain error 2 20 lsb v inl = av ss = 0v, av dd = 3.6v had24a e off offset error 2 10 lsb v inl = av ss = 0v, av dd = 3.6v dynamic performance (12-bit mode) (2) had33a f nyq input signal bandwidth 200 khz note 1: these parameters are characterized, but are tested at 20 ksps only. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 400 ? 2007-2012 microchip technology inc. table 31-16: adc module specifications (10-bit mode) ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic mi n typ max units conditions adc accuracy (10-bit mode) C measurements with external v ref +/v ref - (1) had20b nr resolution (3) 10 data bits bits had21b inl integral nonlinearity -3 3 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had22b dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had23b g err gain error -5 6 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v had24b e off offset error -1 5 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.6v adc accuracy (10-bit mode) C measurements with internal v ref +/v ref - (1) had20b nr resolution (3) 10 data bits bits had21b inl integral nonlinearity -2 2 lsb v inl = av ss = 0v, av dd = 3.6v had22b dnl differential nonlinearity > -1 < 1 lsb v inl = av ss = 0v, av dd = 3.6v had23b g err gain error -5 15 lsb v inl = av ss = 0v, av dd = 3.6v had24b e off offset error -1.5 7 lsb v inl = av ss = 0v, av dd = 3.6v dynamic performance (10-bit mode) (2) had33b f nyq input signal bandwidth 400 khz note 1: these parameters are characterized, but are tested at 20 ksps only. 2: these parameters are characterized by simila rity, but are not tested in manufacturing. 3: injection currents > | 0 | can affect the adc results by approximately 4-6 counts. downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 401 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 table 31-17: adc conversion (12- bit mode) timing requirements table 31-18: adc conversion (10- bit mode) timing requirements ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions clock parameters had50 t ad adc clock period (1) 147 ns conversion rate had56 f cnv throughput rate (1) 400 ksps note 1: these parameters are characterized but not tested in manufacturing. ac characteristics standard operating conditions: 3.0v to 3.6v (unless otherwise stated) operating temperature -40c t a +150c for high temperature param no. symbol characteristic min typ max units conditions clock parameters had50 t ad adc clock period (1) 104 ns conversion rate had56 f cnv throughput rate (1) 8 0 0k s p s note 1: these parameters are characterized but not tested in manufacturing. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 402 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 403 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 32.0 dc and ac device characteristics graphs figure 32-1: v oh C 2x driver pins figure 32-2: v oh C 4x driver pins figure 32-3: v oh C 8x driver pins figure 32-4: v oh C 16x driver pins note: the graphs provided following this note are a statistical summary based on a limited num ber of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs, the data presented may be outside t he specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. -0.016 -0.014 -0.012 -0.010 -0.008 -0.006 -0.004 ioh (a) -0.016 -0.014 -0.012 -0.010 -0.008 -0.006 -0.004 -0.002 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.030 -0.025 -0.020 -0.015 -0.010 ioh (a) -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 ioh (a) -0.040 -0.035 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3v 3.3v 3.6v -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 ioh (a) -0.080 -0.070 -0.060 -0.050 -0.040 -0.030 -0.020 -0.010 0.000 0.00 1.00 2.00 3.00 4.00 ioh (a) voh (v) 3v 3.3v 3.6v downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 404 ? 2007-2012 microchip technology inc. figure 32-5: v ol C 2x driver pins figure 32-6: v ol C 4x driver pins figure 32-7: v ol C 8x driver pins figure 32-8: v ol C 16x driver pins 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 iol (a) 0.000 0.002 0.004 0.006 0.008 0.010 0.012 0.014 0.016 0.018 0.020 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.010 0.015 0.020 0.025 0.030 0.035 0.040 iol (a) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.020 0.030 0.040 0.050 0.060 iol (a) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v 0.040 0.060 0.080 0.100 0.120 iol (a) 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.00 1.00 2.00 3.00 4.00 iol (a) vol (v) 3v 3.3v 3.6v downloaded from: http:/// ? 2007-2012 microchip technology inc. ds70292g-page 405 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 figure 32-9: typical i pd current @ v dd = 3.3v, +85oc figure 32-10: typical i dd current @ v dd = 3.3v, +85oc figure 32-11: typical i doze current @ v dd = 3.3v, +85oc figure 32-12: typical i idle current @ v dd = 3.3v, +85oc 400 600 800 1000 1200 i pd (ua) 0 200 400 600 800 1000 1200 -40-30-20-100 102030405060708090100110120 i pd (ua) temperature (celsius) 20 30 40 50 60 i dd (ma) 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 45 i dd (ma) mips pmd = 0, no pll pmd = 0, with pll pmd = 1, no pll pmd = 1, with pll 20.00 30.00 40.00 50.00 60.00 70.00 80.00 i doze current (ma) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 1:1 2:1 64:1 128:1 i doze current (ma) doze ratio 10 15 20 25 30 35 i idle current (ma) 0 5 10 15 20 25 30 35 10 20 30 40 i idle current (ma) mips downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic 33fj128gpx02/x04 ds70292g-page 406 ? 2007-2012 microchip technology inc. figure 32-13: typical frc frequency @ v dd = 3.3v figure 32-14: typical lprc frequency @ v dd = 3.3v 7200 7300 7400 7500 -40-30-20-100 102030405060708090100110120 frc frequency (khz) temperature (celsius) 30 35 lprc frequency (khz) 25 30 35 -40-30-20-10 0 102030405060708090100110120 lprc frequency (khz) temperature (celsius) downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 407 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 33.0 packaging information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note: if the full microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for custome r-specific information. 3 e 3 e 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example dspic33fj32gp 0730235 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example dspic33fj32gp 0730235 302-e/sp 302-e/so 3 e 3 e xxxxxxxxxx 44-lead qfn xxxxxxxxxxxxxxxxxxxx yywwnnn dspic example -e/ml 0730235 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn 33fj32gp304 example dspic -i/pt 0730235 33fj32gp304 3 e 3 e xxxxxxxx 28-lead qfn-s xxxxxxxxyywwnnn 33fj32gp example 302e/mm0730235 3 e downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 408 ? 2007-2012 microchip technology inc. 33.1 package details 28-lead skinny plastic dual in-line (sp) ? 300 mil body [spdip] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 28 pitch e .100 bsc top to seating plane a ? ? .200 molded package thickness a2 .120 .135 .150 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .335 molded package width e1 .240 .285 .295 overall length d 1.345 1.365 1.400 tip to seating plane l .110 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .050 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 note 1 n 12 d e1 e b c e l a2 e b b1 a1 a 3 microchip technology drawing c04-070b downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 409 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 410 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 411 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 412 ? 2007-2012 microchip technology inc. 28-lead plastic quad flat, no lead package (mm) 6x6x0.9 mm body [qfn-s] with 0.40 mm contact length notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 28 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 6.00 bsc exposed pad width e2 3.65 3.70 4.70 overall length d 6.00 bsc exposed pad length d2 3.65 3.70 4.70 contact width b 0.23 0.38 0.43 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 d e 21 n e2 exposed pad 2 1 d2 n b k l note 1 a3 a a1 to view b otto m view microchip technology drawing c04-124b downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 413 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 !! "# $%& ' ( ) !! *+ + ( , ! " # $ % &"' "" ( $ ) % *++&&&! !+ $ downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 414 ? 2007-2012 microchip technology inc. 44-lead plastic quad flat, no lead package (ml) 8x8 mm body [qfn] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package is saw singulated. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 44 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 8.00 bsc exposed pad width e2 6.30 6.45 6.80 overall length d 8.00 bsc exposed pad length d2 6.30 6.45 6.80 contact width b 0.25 0.30 0.38 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 d exposed pad d2 b k l e2 2 1 n note 1 2 1 e n b otto m view to view a3 a1 a microchip technology drawing c04-103b downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 415 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 )) -(+ . - / / / !! "# !! $- & , ( ,"# %-) # ! , '.# !#" . %& % / !) " " 0"1! , !" " %2 % #%! %) " #" " %) " #" "" -%3!! "% !" % 24 3 5/* 5 "!" - , #" && # " 2 * ) !" '#"# & # ') ) ! # "" , ! " # $ % &"' "" ( $ ) % *++&&&! !+ $ 6 " 772 2 !" 7! " 8 89 : 8#!. )7 %" 8 7 %( ;5/ 9, < = = %%( $ $"" 3 3 % )) 3 = 3 7 7 3 > 3 7 2 ? 3? ? 9, @% 2 5/ 9, 7 5/ %%( $ @% 2 5/ %%( $ 7 5/ 7 % $"" = 7 %@% . 3 % ) ? ? ? % ) 5 ! ? ? ? a e e1 d d1 e b note 1 note 2 n 123 c a1 l a2 l1 & />5 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 416 ? 2007-2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 417 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 appendix a: revision history revision a (september 2007) this is the initial released version of this document. revision b (march 2008) this revision includes minor typographical and formatting changes throughout the data sheet text. in addition, redundant information was removed that is now available in the respective chapters of the dspic33f/pic24h family reference manual , which can be obtained from the microchip website ( www.microchip.com ). the major changes are referenced by their respective section in the following table. table a-1: major section updates section name update description high-performance, 16-bit digital signal controllers note 1 added to all pin diagrams (see pin diagrams ). add external interrupts column and note 3 to the dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 controller families table. section 1.0 device overview updated parameters pma0, pma1, and pmd0 through pmpd7 (table 1-1). section 6.0 inte rrupt controller ifs0-ifso4 changed to ifs x (see section 6.3.2 ifsx ). iec0-iec4 changed to iec x (see section 6.3.3 iecx ). ipc0-ipc19 changed to ipcx (see section 6.3.4 ipcx ). section 7.0 direct memory access (dma) updated parameter pmp (see table 7-1). section 8.0 oscillator configuration updated the third clock source item (external clock) in section 8.1.1 system clock sources. updated tun<5:0> (osctun<5:0>) bit description (see register 8-4). section 20.0 10-bit/12-bit analog-to-digital converter (adc1) added note 2 to figure 20-3. section 26.0 special features added note 2 to figure 26-1. added note after second paragraph in section 26.2 on-chip voltage regulator. section 29.0 electrical characteristics updated max mips for temperature range of -40oc to +125oc in table 29-1. updated typical values in thermal packaging characteristics in table 29-3. added parameters di11 and di12 to table 29-9. updated minimum values for parameters d136 (t rw ) and d137 (t pe ) and removed typical values in table 29-12. added extended temperature range to table 29-13. updated parameter ad63 and added note 3 to table 29-40 and table 29-41. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 418 ? 2007-2012 microchip technology inc. revision c (may 2009) this revision includes minor typographical and formatting changes throughout the data sheet text. global changes include: changed all instances of osci to osc1 and osco to osc2 changed all instances of v ddcore and v ddcore / v cap to v cap /v ddcore the other changes are refe renced by their respective section in the following table. table a-2: major section updates section name update description high-performance, 16-bit digital signal controllers updated all pin diagrams to denote the pin voltage tolerance (see pin diagrams ). added note 2 to the 28-pin qfn-s and 44-pin qfn pin diagrams, which references pin connections to v ss . section 1.0 device overview updated av dd in the pinout i/o descriptions (see table 1-1). added peripheral pin select (pps) capability column to pinout i/o descriptions (see table 1-1). section 2.0 guidelines for getting started with 16-bit digital signal controllers added new section to the data sheet t hat provides guidelines on getting started with 16-bit digital signal controllers. section 3.0 cpu updated cpu core block diagram with a connection from the dsp engine to the y data bus (see figure 3-1). vertically extended the x and y data bus lines in the dsp engine block diagram (see figure 3-3). section 4.0 memory organization updated reset value for corcon in the cpu core register map (see table 4-1). updated the reset values for ipc14 and ipc15 and removed the flta1ie bit (iec3) from the interrupt cont roller register map (see table 4-4). updated bit locations for rpinr25 in the peripheral pin select input register map (see table 4-21). updated the reset value for clkdiv in the system control register map (see table 4-33). section 5.0 flash program memory updated section 5.3 programming operations with programming time formula. section 9.0 oscillator configuration updated the oscillator system diagram and added note 2 (see figure 9-1). added note 1 and note 2 to the oscon register (see register 9-1). updated default bit values for doze<2:0> and frcdiv<2:0> in the clock divisor (clkdiv) register (see register 9-2). added a paragraph regarding frc accuracy at the end of section 9.1.1 system clock sources . added note 3 to section 9.2.2 oscillator switching sequence . added note 1 to the frc oscillator tuning (osctun) register (see register 9-4). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 419 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 section 10.0 power-saving features added the following registers: pmd1: peripheral module disable control register 1 (register 10-1) pmd2: peripheral module disable control register 2 (register 10-2) pmd3: peripheral module disable control register 3 (register 10-3) section 11.0 i/o ports removed table 11-1 and added reference to pin diagrams for i/o pin availability and functionality. added paragraph on adpcfg register default values to section 11.3 configuring analog port pins . added note box regarding pps functionality with input mapping to section 11.6.2.1 input mapping . section 16.0 serial peripheral interface (spi) added note 2 and 3 to the spixcon1 register (see register 16-2). section 18.0 universal asynchronous receiver transmitter (uart) updated the notes in the uxmode register (see register 18-1). updated the utxinv bit settings in the uxsta register and added note 1 (see register 18-2). section 19.0 enhanced can (ecan?) module changed bit 11 in the ecan control register 1 (cictrl1) to reserved (see register 19-1). section 21.0 10-bit/12-bit analog- to-digital converter (adc) replaced the adc1 module block diagrams with new diagrams (see figure 21-1 and figure 21-2). updated bit values for adcs<7:0> and added notes 1 and 2 to the adc1 control register 3 (ad1con3) (see register 21-3). added note 2 to the adc1 input scan select register low (ad1cssl) (see register 21-7). added note 2 to the adc1 port configuration register low (ad1pcfgl) (see register 21-8). section 22.0 audio digital-to- analog converter (dac) updated the midpoint voltage in the la st sentence of the first paragraph. updated the voltage swing values in the last sentence of the last paragraph in section 22.3 dac output format . section 23.0 comparator module updated the comparator voltage reference block diagram (see figure 23-2). section 24.0 real-time clock and calendar (rtcc) updated the minimum positive adjust value for cal<7:0> in the rtcc calibration and configuration (rcfgcal) register (see register 24-1). section 27.0 special features added note 1 to the device configuration register map (see table 27-1). updated note 1 in the dspic33f conf iguration bits description (see table 27-2). table a-2: major section updates (continued) section name update description downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 420 ? 2007-2012 microchip technology inc. section 30.0 electrical characteristics updated typical values for thermal packaging characteristics (see table 30-3). updated min and max values for parameter dc12 (ram data retention voltage) and added note 4 (see table 30-4). updated power-down current max va lues for parameters dc60b and dc60c (see table 30-7). updated characteristics for i/o pi n input specifications and added parameter di21 (see table 30-9). updated program memory values for parameters 136, 137, and 138 (renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and 138b, and added note 2 (see table 30-12). added parameter os42 (g m ) to the external clock timing requirements (see table 30-16). updated watchdog timer time-out period parameter sy20 (see table 30-21). updated the i ref current drain parameter ad08 (see table 30-37). updated parameters ad30a, ad3 1a, ad32a, ad33a, and ad34a (see table 30-38) updated parameters ad30b, ad3 1b, ad32b, ad33b, and ad34b (see table 30-39) table a-2: major section updates (continued) section name update description downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 421 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 revision d (november 2009) the revision includes the following global update: added note 2 to the shaded table that appears at the beginning of each chapter. this new note provides information regarding the availability of registers and their associated bits this revision also includes minor typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. table a-3: major section updates section name update description high-performance, 16-bit digital signal controllers added information on high temperature operation (see operating range: ). section 11.0 i/o ports changed the reference to digital-only pins to 5v tolerant pins in the second paragraph of section 11.2 open-drain configuration . section 18.0 universal asynchronous receiver transm itter (uart) updated the two baud rate range features to: 10 mbps to 38 bps at 40 mips. section 21.0 10-bit/12-bit analog-to-digital converter (adc) updated the adc block diagrams (see figure 21-1 and figure 21-2). section 22.0 audio digital-to-analog converter (dac) removed last sentence of the first paragraph in the section. added a shaded note to section 22.2 dac module operation . updated figure 22-2: audio dac output for ramp input (unsigned). section 27.0 special features updated the second paragraph and removed the fourth paragraph in section 27.1 configuration bits . updated the device configuratio n register map (see table 27-1). section 30.0 electrical characteristics updated the absolute maximum ratings for high temperature and added note 4. removed parameters di26, di28, and di29 from the i/o pin input specifications (see table 30-9). updated the spix module slave mode (cke = 1 ) timing characteristics (see figure 30-12). removed table 30-43: audio dac m odule specifications. original contents were updated and combined with table 30-42 of the same name. section 31.0 high temperature electrical characteristics added new chapter with high temperature specifications. product identification system added the h definition for high temperature. downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 422 ? 2007-2012 microchip technology inc. revision e (january 2011) this includes typographical and formatting changes throughout the data sheet text. in addition, the preliminary marking in the footer was removed. all instances of v ddcore have been removed. all other major changes are referenced by their respective section in the following table. table a-4: major section updates section name update description high-performance, 16-bit digital signal controllers the high temperature end range was updated to +150oc (see operating range: ). section 2.0 guidelines for getting started with 16-bit digital signal controllers updated the title of section 2.3 cpu logic filter capacitor connection (v cap ) . the frequency limitation for device pll start-up conditions was updated in section 2.7 oscillator valu e conditions on device start-up . the second paragraph in section 2.9 unused i/os was updated. section 4.0 memory organization the all resets values for the following sfrs in the timer register map were changed (see table 4-5): tmr1 tmr2 tmr3 tmr4 tmr5 section 9.0 oscillator configuration added note 3 to the osccon: osci llator control register (see register 9-1). added note 2 to the clkdiv: clock divisor register (see register 9-2). added note 1 to the pllfbd: pll feedback divisor register (see register 9-3). added note 2 to the osctun: frc oscillator tuning register (see register 9-4). added note 1 to the aclkcon: auxiliary control register (see register 9-5). section 21.0 10-bit/12-b it analog-to-digital converter (adc) updated the v refl references in the adc1 module block diagrams (see figure 21-1 and figure 21-2). section 27.0 special features added a new paragraph and removed the third paragraph in section 27.1 configuration bits . added the column rtsp effects to the dspic33f configuration bits descriptions (see table 27-2). downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 423 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 section 30.0 electrical characteristics updated the maximum value for extended temperature devices in the thermal operating conditions (see table 30-2). removed note 4 from the dc temperature and voltage specifications (see table 30-4). updated all typical and maximum operating current (i dd ) values (see table 30-5). updated all typical and maximum idle current (i idle ) values (see table 30-6). updated the maximum power-down current (i pd ) values for parameters dc60d, dc60a, and dc60b (see table 30-7). updated all typical doze current (idoze) values (see table 30-8). updated the maximum value for parameter di19 and added parameters di28, di29, di60a, di60b , and di60c to the i/o pin input specifications (see table 30-9). removed note 2 from the ac characteristics: internal rc accuracy (see table 30-18). added note 2 to the pll clock timing specifications (see table 30-17) updated the internal rc accuracy minimum and maximum values for parameter f21b (see table 30-19). updated the characteristic description for parameter di35 in the i/o timing requirements (see table 30-20). updated all spi specifications (see table 30-28 through table 30-35 and figure 30-9 through figure 30-16) updated the adc module specification minimum values for parameters ad05 and ad07, and updated the maximum value for parameter ad06 (see table 30-41). updated the adc module specifications (12-bit mode) minimum and maximum values for parameter ad21a (see table 30-42). updated all adc module specificat ions (10-bit mode) values, with the exception of dynamic pe rformance (see table 30-43). updated the minimum value for parameter pm6 and the maximum value for parameter pm7 in the parallel master port read timing requirements (see table 30-52). added dma read/write timing requirements (see table 30-54). table a-4: major section updates (continued) section name update description downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 424 ? 2007-2012 microchip technology inc. section 31.0 high temperature electrical characteristics updated all ambient temperatur e end range values to +150oc throughout the chapter. updated the storage temper ature end range to +160oc. updated the maximum junction tem perature from +145oc to +155oc. updated the maximum values for high temperature devices in the thermal operating conditions (see table 31-2). updated the adc module specific ations (12-bit mode) (see table 31-14). updated the adc module specific ations (10-bit mode) (see table 31-15). product identification system updated the end range temperatur e value for h (high) devices. table a-4: major section updates (continued) section name update description downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 425 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 revision f (august 2011) this revision includes typographical and formatting changes throughout the data sheet text. all other major changes are referenced by their respective section in the following table. revision g (april 2012) this revision includes typographical and formatting changes throughout the data sheet text. in addition, where applicable, new sections were added to each peripheral chapter th at provide information and links to related resources, as well as helpful tips. for examples, see section 9.2 oscillator resources and section 21.4 adc helpful tips . all other major changes are referenced by their respective section in the following table. table a-5: major section updates section name update description section 2.0 guidelines for getting started with 16-bit digital signal controllers updated the recommendation minimum connection (see figure 2-1). section 27.0 special features added note 3 to the connections for the on-chip voltage regulator diagram (see figure 27-1). section 30.0 electrical characteristics removed voltage on v cap with respect to vss from the absolute maximum ratings. removed note 3 and parameter dc10 (v core ) from the dc temperature and voltage specifications (see table 30-4). updated the characteristics definition and conditions for parameter bo10 in the electrical characteristics: bor (see table 30-11). added note 1 to the internal volt age regulator specifications (see table 30-13). table a-6: major section updates section name update description section 2.0 guidelines for getting started with 16-bit digital signal controllers added two new tables: crystal recommendations (see table 2-1 ) resonator recommendations (see table 2-2 ) section 30.0 electrical characteristics updated parameters do10 and do20 and removed parameters do16 and do26 in the dc characteristics: i/o pin output specifications (see table 30-10 ) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 426 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 427 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 index a ac characteristics .................................................... 349, 396 adc module.............................................................. 399 adc module (10-bit mode) ....................................... 400 adc module (12-bit mode) ....................................... 399 internal rc accuracy ................................................ 351 load conditions ................................................ 349, 396 alternate interrupt vector table (aivt) .............................. 87 analog-to-digital converter............................................... 263 adc1 register map .................................................... 49 dma .......................................................................... 263 initialization ............................................................... 263 key features............................................................. 263 arithmetic logic unit (alu)................................................. 30 assembler mpasm assembler................................................... 334 b barrel shifter ....................................................................... 34 bit-reversed addressing .................................................... 64 example ...................................................................... 65 implementation ........................................................... 64 sequence table (16-entry)......................................... 65 block diagrams 16-bit timer1 module ................................................ 189 adc1 module.................................................... 264, 265 connections for on-chip voltage regulator............. 319 dci module ............................................................... 255 device clock ..................................................... 141, 143 dsp engine ................................................................ 31 dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 .......................... 14 dspic33fj32gp302/304, dspic33fj64gpx02/x04, and dspic33fj128gpx02/x04 cpu core......... 24 ecan module ........................................................... 229 input capture ............................................................ 199 output compare ....................................................... 203 pll............................................................................ 143 reset system.............................................................. 77 shared port structure ............................................... 159 spi ............................................................................ 207 timer2 (16-bit) .......................................................... 193 timer2/3 (32-bit) ....................................................... 195 uart ........................................................................ 221 watchdog timer (wdt) ............................................ 320 cc compilers mplab c18 .............................................................. 334 clock switching................................................................. 151 enabling .................................................................... 151 sequence.................................................................. 151 code examples erasing a program memory page............................... 75 initiating a programming sequence............................ 76 loading write buffers ................................................. 76 port write/read ........................................................ 160 pwrsav instruction syntax..................................... 153 code protection ........................................................ 315, 321 comparator module .......................................................... 277 configuration bits.............................................................. 315 configuration register map .............................................. 315 configuring analog port pins ............................................ 160 cpu control register .......................................................... 27 cpu clocking system ...................................................... 142 pll configuration..................................................... 143 selection................................................................... 142 sources .................................................................... 142 customer change notification service............................. 431 customer notification service .......................................... 431 customer support............................................................. 431 d data accumulators and adder/subtracter .......................... 32 data space write saturation ...................................... 34 overflow and saturation ............................................. 32 round logic ............................................................... 33 write back .................................................................. 33 data address space........................................................... 37 alignment.................................................................... 37 memory map for dspic33fj128gp202/204 and dspic33fj64gp202/204 devices with 8 kb ram...................................... 39 memory map for dspic33fj128gp802/804 and dspic33fj64gp802/804 devices with 16 kb ram.................................... 40 memory map for dspic33fj32gp302/304 devices with 4 kb ram ................................................... 38 near data space ........................................................ 37 software stack ........................................................... 61 width .......................................................................... 37 data converter interface (dci) module ............................ 255 dc and ac characteristics graphs and tables ................................................... 403 dc characteristics............................................................ 338 doze current (i doze )................................................ 393 high temperature..................................................... 392 i/o pin input specifications ...................................... 344 i/o pin output specifications............................ 347, 394 idle current (i doze ) .................................................. 343 idle current (i idle ) .................................................... 341 operating current (i dd ) ............................................ 340 operating mips vs. voltage ..................................... 392 power-down current (i pd )........................................ 342 power-down current (i pd ) ........................................ 393 program memory.............................................. 348, 395 temperature and voltage......................................... 392 temperature and voltage specifications.................. 339 thermal operating conditions.................................. 392 dci introduction............................................................... 255 dci module register map .............................................................. 54 development support ....................................................... 333 dma module dma register map ..................................................... 50 dmac registers ............................................................... 131 dmaxcnt ................................................................ 131 dmaxcon................................................................ 131 dmaxpad ................................................................ 131 dmaxreq ................................................................ 131 dmaxsta................................................................. 131 dmaxstb................................................................. 131 doze mode ....................................................................... 154 dsp engine ........................................................................ 30 multiplier ..................................................................... 32 e ecan module cibufpnt1 register................................................. 241 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 428 ? 2007-2012 microchip technology inc. cibufpnt2 register ................................................. 242 cibufpnt3 register ................................................. 242 cibufpnt4 register ................................................. 243 cicfg1 register ........................................................ 239 cicfg2 register ........................................................ 240 cictrl1 register ...................................................... 232 cictrl2 register ...................................................... 233 ciec register............................................................. 239 cifctrl register ...................................................... 235 cifen1 register ........................................................ 241 cififo register ......................................................... 236 cifmsksel1 register ............................................... 245 cifmsksel2 register ............................................... 246 ciinte register ......................................................... 238 ciintf register.......................................................... 237 cirxfneid register .................................................. 245 cirxfnsid register .................................................. 244 cirxful1 register .................................................... 248 cirxful2 register .................................................... 248 cirxmneid register.................................................. 247 cirxmnsid register.................................................. 247 cirxovf1 register ................................................... 249 cirxovf2 register ................................................... 249 citrmncon register ................................................ 250 civec register .......................................................... 234 ecan1 register map (c1ctrl1.win = 0 or 1) ......... 52 ecan1 register map (c1ctrl1.win = 0) ................ 52 ecan1 register map (c1ctrl1.win = 1) ................ 53 frame types ............................................................. 228 modes of operation .................................................. 230 overview ................................................................... 227 ecan registers acceptance filter enable register (cifen1)............ 241 acceptance filter extended identifier register n (cirxfneid) ..................................................... 245 acceptance filter mask extended identifier register n (cirxmneid) .................................................... 247 acceptance filter mask standard identifier register n (cirxmnsid) .................................................... 247 acceptance filter standard identifier register n (cirxfnsid) ..................................................... 244 baud rate configuration register 1 (cicfg1) ......... 239 baud rate configuration register 2 (cicfg2) ......... 240 control register 1 (cictrl1) ................................... 232 control register 2 (cictrl2) ................................... 233 fifo control register (cifctrl) ............................ 235 fifo status register (cififo) ................................. 236 filter 0-3 buffer pointer register (cibufpnt1) ....... 241 filter 12-15 buffer pointer register (cibufpnt4) ... 243 filter 15-8 mask selection register (cifmsksel2). 246 filter 4-7 buffer pointer register (cibufpnt2) ....... 242 filter 7-0 mask selection register (cifmsksel1)... 245 filter 8-11 buffer pointer register (cibufpnt3) ..... 242 interrupt code register (civec) .............................. 234 interrupt enable register (ciinte) ........................... 238 interrupt flag register (ciintf) ............................... 237 receive buffer full register 1 (cirxful1).............. 248 receive buffer full register 2 (cirxful2).............. 248 receive buffer overflow r egister 2 (cirxovf2)..... 249 receive overflow register (cirxovf1) .................. 249 ecan transmit/receive error count register (ciec) ..... 239 ecan tx/rx buffer m control register (citrmncon) .. 250 electrical characteristics................................................... 337 ac ..................................................................... 349, 396 enhanced can module..................................................... 227 equations device operating frequency .................................... 142 errata .................................................................................. 11 f flash program memory ...................................................... 71 control registers ........................................................ 72 operations .................................................................. 72 programming algorithm .............................................. 75 rtsp operation ......................................................... 72 table instructions ....................................................... 71 flexible configuration ....................................................... 315 h high temperature electrical characteristics .................... 391 i i/o ports............................................................................ 159 parallel i/o (pio) ...................................................... 159 write/read timing .................................................... 160 i 2 c operating modes ...................................................... 213 registers .................................................................. 215 in-circuit debugger........................................................... 321 in-circuit emulation .......................................................... 315 in-circuit serial programming (icsp)....................... 315, 321 input capture .................................................................... 199 registers .................................................................. 201 input change notification ................................................. 160 instruction addressing modes ............................................ 61 file register instructions ............................................ 61 fundamental modes supported ................................. 62 mac instructions ........................................................ 62 mcu instructions ........................................................ 61 move and accumulator instructions............................ 62 other instructions ....................................................... 62 instruction set overview................................................................... 328 summary .................................................................. 325 instruction-based power-saving modes........................... 153 idle ............................................................................ 154 sleep ........................................................................ 153 internal rc oscillator use with wdt........................................................... 320 internet address ............................................................... 431 interrupt control and status registers ............................... 91 iecx ............................................................................ 91 ifsx ............................................................................ 91 intcon1 .................................................................... 91 intcon2 .................................................................... 91 ipcx ............................................................................ 91 interrupt setup procedures............................................... 127 initialization ............................................................... 127 interrupt disable ....................................................... 127 interrupt service routine .......................................... 127 trap service routine ................................................ 127 interrupt vector table (ivt) ................................................ 87 interrupts coincident with power save instructions ......... 154 j jtag boundary scan interface ........................................ 315 jtag interface.................................................................. 321 m memory organization ......................................................... 35 microchip internet web site.............................................. 431 modes of operation disable...................................................................... 230 initialization ............................................................... 230 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 429 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 listen all messages .................................................. 230 listen only ................................................................ 230 loopback .................................................................. 230 normal operation...................................................... 230 modulo addressing ............................................................. 63 applicability ................................................................. 64 operation example ..................................................... 63 start and end address................................................ 63 w address register selection .................................... 63 mplab asm30 assembler, linker, librarian ................... 334 mplab integrated development environment software .. 333 mplab pm3 device programmer .................................... 336 mplab real ice in-circuit emulator system................. 335 mplink object linker/mplib object librarian ................ 334 n nvm module register map............................................................... 60 o open-drain configuration ................................................. 160 output compare ............................................................... 203 p packaging ......................................................................... 407 marking ..................................................................... 407 peripheral module disable (pmd) .................................... 154 pinout i/o descriptions (table) ............................................ 15 pmd module register map............................................................... 60 porta register map......................................................... 58, 59 portb register map............................................................... 59 power-on reset (por) ....................................................... 83 power-saving features .................................................... 153 clock frequency and switching................................ 153 program address space ..................................................... 35 construction................................................................ 66 data access from program memory using program space visibility ..................................... 69 data access from program memory using table instructions ............................................... 68 data access from, ad dress generation...................... 67 memory map ............................................................... 35 table read instructions tblrdh ............................................................. 68 tblrdl .............................................................. 68 visibility operation ...................................................... 69 program memory interrupt vector ........................................................... 36 organization................................................................ 36 reset vector ............................................................... 36 r reader response ............................................................. 432 register map crc ............................................................................ 58 dual comparator......................................................... 58 parallel master/slave port .......................................... 57 real-time clock and calendar................................... 58 registers ad1chs0 (adc1 input channel 0 select ................ 274 ad1chs123 (adc1 input channel 1, 2, 3 select) ... 273 ad1con1 (adc1 control 1) .................................... 268 ad1con2 (adc1 control 2) .................................... 270 ad1con3 (adc1 control 3) .................................... 271 ad1con4 (adc1 control 4) .................................... 272 ad1cssl (adc1 input scan select low) ............... 275 ad1pcfgl (adc1 port configuration low) ............ 275 cibufpnt1 (ecan filter 0-3 buffer pointer) .......... 241 cibufpnt2 (ecan filter 4-7 buffer pointer) .......... 242 cibufpnt3 (ecan filter 8-11 buffer pointer) ........ 242 cibufpnt4 (ecan filter 12-15 buffer pointer) ...... 243 cicfg1 (ecan baud rate configuration 1)............ 239 cicfg2 (ecan baud rate configuration 2)............ 240 cictrl1 (ecan control 1)...................................... 232 cictrl2 (ecan control 2)...................................... 233 ciec (ecan transmit/receive error count) ........... 239 cifctrl (ecan fifo control) ............................... 235 cifen1 (ecan acceptance filter enable)............... 241 cififo (ecan fifo status) .................................... 236 cifmsksel1 (ecan filter 7- 0 mask selection) .... 245, 246 ciinte (ecan interrupt enable) .............................. 238 ciintf (ecan interrupt flag) .................................. 237 cirxfneid (ecan acceptance filter n extended identifier) .......................................... 245 cirxfnsid (ecan acceptance filter n standard identifier) ........................................... 244 cirxful1 (ecan receive buffer full 1)................. 248 cirxful2 (ecan receive buffer full 2)................. 248 cirxmneid (ecan acceptance filter mask n extended identifier) .......................................... 247 cirxmnsid (ecan acceptance filter mask n standard identifier) ........................................... 247 cirxovf1 (ecan receive buffer overflow 1)........ 249 cirxovf2 (ecan receive buffer overflow 2)........ 249 citrbnsid (ecan buffer n standard identifier)..... 251, 252, 254 citrmncon (ecan tx/rx buffer m control) ........ 250 civec (ecan interrupt code) ................................. 234 clkdiv (clock divisor) ............................................ 147 corcon (core control)...................................... 29, 92 dcicon1 (dci control 1) ........................................ 257 dcicon2 (dci control 2) ........................................ 258 dcicon3 (dci control 3) ........................................ 259 dcistat (dci status) ............................................. 260 dmacs0 (dma controller status 0) ........................ 136 dmacs1 (dma controller status 1) ........................ 138 dmaxcnt (dma channel x transfer count)........... 135 dmaxcon (dma channel x control)....................... 132 dmaxpad (dma channel x peripheral address) .... 135 dmaxreq (dma channel x irq select) ................. 133 dmaxsta (dma channel x ram start address a) . 134 dmaxstb (dma channel x ram start address b) . 134 dsadr (most recent dma ram address) ............. 139 i2cxcon (i2cx control)........................................... 216 i2cxmsk (i2cx slave mode address mask)............ 220 i2cxstat (i2cx status) ........................................... 218 ifs0 (interrupt flag status 0) ............................. 96, 103 ifs1 (interrupt flag status 1) ............................. 98, 105 ifs2 (interrupt flag status 2) ........................... 100, 107 ifs3 (interrupt flag status 3) ........................... 101, 108 ifs4 (interrupt flag status 4) ........................... 102, 109 intcon1 (interrupt control 1) ................................... 93 intcon2 (interrupt control 2) ................................... 95 inttreg interrupt control and status register ...... 126 ipc0 (interrupt priority control 0) ............................. 110 ipc1 (interrupt priority control 1) ............................. 111 ipc11 (interrupt priority control 11) ......................... 120 ipc14 (interrupt priority control 14) ......................... 121 ipc15 (interrupt priority control 15) ......................... 122 ipc16 (interrupt priority control 16) ......................... 123 downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 430 ? 2007-2012 microchip technology inc. ipc17 (interrupt priority control 17) ......................... 124 ipc18 (interrupt priority control 18) ......................... 125 ipc2 (interrupt priority control 2) ............................. 112 ipc3 (interrupt priority control 3) ............................. 113 ipc4 (interrupt priority control 4) ............................. 114 ipc5 (interrupt priority control 5) ............................. 115 ipc6 (interrupt priority control 6) ............................. 116 ipc7 (interrupt priority control 7) ............................. 117 ipc8 (interrupt priority control 8) ............................. 118 ipc9 (interrupt priority control 9) ............................. 119 nvmcon (flash memory control) ............................. 73 nvmkey (nonvolatile memory key) .......................... 74 ocxcon (output compare x control) ..................... 206 osccon (oscillator control) ................................... 145 osctun (frc oscillat or tuning) ............................ 149 pllfbd (pll feedback divisor) .............................. 148 pmd1 (peripheral module disable control register 1)............................................ 156 pmd2 (peripheral module disable control register 2)............................................ 157 pmd3 (peripheral module disable control register 3)............................................ 158 pxtcon (pwm time base control)......... 280, 281, 282 rcon (reset control) ................................................ 79 rscon (dci receive slot control).......................... 261 spixcon1 (spix control 1) ...................................... 210 spixcon2 (spix control 2) ...................................... 212 spixstat (spix status and control) ....................... 209 sr (cpu status) ................................................... 27, 92 t1con (timer1 control)........................................... 191 tcxcon (input capture x control) ........................... 201 tscon (dci transmit slot control) ......................... 261 txcon (type b time base control) ........................ 196 tycon (type c time base control) ........................ 197 uxmode (uartx mode) .......................................... 223 uxsta (uartx status and control) ......................... 225 reset illegal opcode ....................................................... 77, 85 trap conflict.......................................................... 84, 85 uninitialized w register ........................................ 77, 85 reset sequence.................................................................. 87 resets ................................................................................. 77 s serial peripheral interface (spi) ....................................... 207 software reset instruction (swr) ...................................... 84 software simulator (mplab sim)..................................... 335 software stack pointer, frame pointer calll stack frame.................................................... 61 special features of the cpu............................................. 315 spi module spi1 register map ...................................................... 48 symbols used in opcode descriptions............................. 326 system control register map............................................................... 60 t temperature and voltage specifications ac ..................................................................... 349, 396 timer1 ............................................................................... 189 timer2/3 ............................................................................ 193 timing characteristics clko and i/o ........................................................... 352 timing diagrams 10-bit adc (chps<1:0> = 01, simsam = 0, asam = 0, ssrc<2:0> = 000) ........................................... 385 10-bit adc (chps<1:0> = 01, simsam = 0, asam = 1, ssrc<2:0> = 111, samc<4:0> = 00001)....................................... 385 12-bit adc (asam = 0, ssrc<2:0> = 000) ........................................... 383 brown-out situations................................................... 84 dci ac-link mode.................................................... 377 dci multi -channel, i 2 s modes................................. 375 ecan i/o .................................................................. 379 external clock........................................................... 350 i2cx bus data (master mode) .................................. 371 i2cx bus data (slave mode) .................................... 373 i2cx bus start/stop bits (master mode)................... 371 i2cx bus start/stop bits (slave mode)..................... 373 input capture (capx) ............................................... 357 oc/pwm................................................................... 358 output compare (ocx)............................................. 357 reset, watchdog timer, oscillator start-up timer and power-up timer ......................................... 353 timer1, 2 and 3 external clock ................................ 355 timing requirements adc conversion (10- bit mode)................................. 401 adc conversion (12- bit mode)................................. 401 clko and i/o ........................................................... 352 dci ac-link mode.................................................... 378 dci multi-channel, i 2 s modes.................................. 376 external clock........................................................... 350 input capture ............................................................ 357 spix master mode (cke = 0) ................................... 397 spix module master mode (cke = 1) ...................... 397 spix module slave mode (cke = 0) ........................ 398 spix module slave mode (cke = 1) ........................ 398 timing specifications 10-bit adc conversion requirements...................... 386 12-bit adc conversion requirements...................... 384 can i/o requirements ............................................. 379 i2cx bus data requirements (master mode)........... 372 i2cx bus data requirements (slave mode)............. 374 output compare requirements................................ 357 pll clock ......................................................... 351, 396 qei external clock requirements ............................ 356 qei index pulse requirements ................................ 358 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements......................................... 354 simple oc/pwm mode requirements ..................... 358 timer1 external clock requirements ....................... 355 timer2 external clock requirements ....................... 356 timer3 external clock requirements ....................... 356 u uart module uart1 register map............................................ 47, 48 universal asynchronous receiver transmitter (uart) ... 221 using the rcon status bits............................................... 85 v voltage regulator (on-chip) ............................................ 319 w watchdog time-out reset (wdtr).................................... 84 watchdog timer (wdt)............................................ 315, 320 programming considerations ................................... 320 www address ................................................................. 431 www, on-line support ..................................................... 11 downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 431 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 432 ? 2007-2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds70292g dspic33fj32gp302/304, ds pic33fj64gpx02/x04, and dspic33fj128gpx02/x04 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 433 dspic33fj32gp302/304, ds pic33fj64gpx02/x04, a nd dspic33fj128gpx02/x04 product identification system to order or obtain information, e.g., on pricing or deliv ery, refer to the factory or the listed sales office . architecture: 33 = 16-bit digital signal controller flash memory family: fj = flash program memory, 3.3v product group: gp2 = general purpose family gp3 = general purpose family gp8 = general purpose family pin count: 02 = 28-pin 04 = 44-pin temperature range: i = -40 c to+85 c (industrial) e=- 4 0 c to+125 c (extended) h=- 4 0 c to+150 c (high) package: sp = skinny plastic dual in-line - 300 mil body (spdip) so = plastic small outline - wide - 7.5 mil body (soic) ml = plastic quad, no lead package - 8x8 mm body (qfn) mm = plastic quad, no lead package - 6x6x0.9 mm body (qfn-s) pt = plastic thin quad flatpack - 10x10x1 mm body (tqfp) examples: a) dspic33fj32gp302-e/sp: general purpose dspic33, 32 kb program memory, 28-pin, extended temperature, spdip package. microchip trademark architecture flash memory family program memory size (kb) product group pin count temperature range package pattern dspic 33 fj 32 gp3 0 2 t e / sp - xxx tape and reel flag (if applicable) downloaded from: http:/// dspic33fj32gp302/304, dspic33fj64gpx02/ x04, and dspic33fj128gpx02/x04 ds70292g-page 434 ? 2007-2012 microchip technology inc. notes: downloaded from: http:/// ? 2007-2012 microchip tec hnology inc. ds70292g-page 435 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007-2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-235-6 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality ? management ? ? s ystem ? certified ? by ? dnv ? == iso/ts ? 16949 ? == ? downloaded from: http:/// ds70292g-page 436 ? 2007-2012 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto 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